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F. Darlay

dblp:62/5891 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › design for testability
built-in self-test
0.011995
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors · IEEE Trans. Computers 1995
Electronic design automation
hardware verification and test
0.011995
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors · IEEE Trans. Computers 1995
Electronic design automation › hardware verification and test › random testing
pseudorandom testing
0.011995
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors · IEEE Trans. Computers 1995
Electronic design automation › hardware verification and test
sequential circuit testing
0.011995
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors · IEEE Trans. Computers 1995
Electronic design automation › hardware verification and test
test generation
0.011995
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors · IEEE Trans. Computers 1995

Methods — techniques the papers use, named apart from their topics

markov chain model · 0.0
YearPublicationVenuePosition
1995 Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors
abstract
In this paper, the initialization of sequential circuits using pseudorandom input patterns is addressed. An extended Markov chain model that covers the initialization phase is proposed. This model supports the theoretical framework used to demonstrate that sequential circuits can be initialized with pseudorandom vectors. This leads to a uniform BIST approach in which initialization and testing are performed together with a single pseudorandom generator.>
Mohamed Soufi, Yvon Savaria, F. Darlay, Bozena Kaminska
IEEE Trans. Computers3