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Atsuo Itoh

dblp:62/5918 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 56% Integrated circuit design · 44%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › switch architecture
ATM switch		 0.011991
Practical Implementation and Packaging Technologies for a Large-Scale ATM Switching System · IEEE J. Sel. Areas Commun. 1991
Integrated circuit design
VLSI design		 0.011991
Practical Implementation and Packaging Technologies for a Large-Scale ATM Switching System · IEEE J. Sel. Areas Commun. 1991

Methods — techniques the papers use, named apart from their topics

orthogonal packaging · 0.0bit-slice techniques · 0.0
YearPublicationVenuePosition
1991 Practical Implementation and Packaging Technologies for a Large-Scale ATM Switching System
abstract
The practical implementation of a trial large-scale asynchronous transfer mode (ATM) switching system and its packaging technologies are described. The architecture of the ATM switching system is discussed with an emphasis on system scalability. A building block architecture in which switching capacity can be expanded in a modular fashion is introduced. The design of the ATM switching system, including the ATM switch element, is described. The implementation of the VLSIs for the ATM switch which realize a highly modular system is explained. Bit-slice techniques are effectively used to realize a high-speed switch element as a CMOS VLSI chipset. An edge-to-edge orthogonal packaging technique is also presented.>
Atsuo Itoh, Hiroshi Nagano, Masaru Kurisaka, Susumu Iwasaki
 IEEE J. Sel. Areas Commun.1