Modern circuit placement, especially analog placement, often needs to consider various constraints, such as symmetry, proximity, preplaced, variant, fixed-boundary, minimum separation, boundary, and fixed-outline constraints, for better electrical effects and higher performance. To handle these diverse constraints, topological floorplan representations are pervasively used because of their higher flexibility and smaller solution space. Due to their intrinsic limitation in deriving module adjacency information directly from the representations themselves, however, they might incur difficulties in handling related constraints. In this paper, we work on B*-trees, which have been shown to be most effective and efficient for floor-plan/placement problems, and present a corner stitching compliant B*-tree (CB-tree, for short) to remedy the significant deficiency in its module adjacency handling. A CB-tree is a B*-tree integrated with modified corner stitching to offer much higher flexibility/efficiency, especially for adjacent module identification/packing. Compared with the previous works, CB-trees can achieve the lowest time complexity for module packing with the aforementioned constraints. Experimental results show that the CB-trees achieve the best solution quality and consume the least running time for industrial designs with various constraints. In particular, our work provides key insights into the handling of comprehensive placement constraints with a topological representation.

Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design verification. Using an emulator, designers can realize designs through a software configuration process and perform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multiphase design tasks, which is a very time-consuming process. Hence, shortening the time to emulation is always the main concern for the logic-emulation design process. One approach to shorten the design processing time is to replace portions of the design with macro cells. This paper presents a module generator for logic-emulation applications, which is able to generate macro cells of arbitrarily complex functions described in hardware descriptive languages. Furthermore, the module generator can effectively generate a multiple field-programmable gate array (FPGA) macro for large macros that cannot fit in a single FPGA chip. Experiments using the module generator for logic emulation are reported. The results demonstrate that the module generator can effectively and efficiently generate complex macros from their register transfer-level description. In addition, the results also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.

Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design verification. Using an emulator, designers can realize designs through a software configuration process and perform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multi-phase design tasks, which is a very time-consuming process. Hence, shortening the Time-To-Emulation (TTE) is always the main concern for the logic-emulation design process. One approach t o shorten the design processing time is to replace portions of the design with macro cells. This paper presents a module generator for logic-emulation applications, which is able to generate macro cells of arbitrarily complex functions described in High-level Descriptive Languages the (HDLs), Furthermore, the module generator can effectively generate a multiple-FPGA macro for large macros which can not fit in a single FPGA chip. Experiments using the module generator for logic emulation are reported. The results demonstrate that the module generator can effectively and efficiently generate complex macros from their Register-Transfer-Level (RTL) description. In addition, the results also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.

This paper treats the automatic translation of register transfer level (RTL) descriptions of digital systems to VLSI realization. The target technology is the storage logic array or SLA. The approach is aimed at applications where the emphasis is on reducing engineering effort and design turnaround time rather than maximizing chip area utilization. The paper develops a mapping between the register transfer language, AHPL, and the SLA. It is shown that each primitive explicitly appearing in an AHPL description can be mapped into an area of real estate in an SLA realization. A detailed development of some of the algorithms is presented. The entire process has been successfully implemented and applied to a set of examples. This is accomplished by developing a final stage for an already existing three-stage multi-application compiler for AHPL. Layout and routing are shown to be a single optimization process if the hardware target is an SLA.