Semantic segmentation is one of the popular tasks in computer vision, providing pixel-wise annotations for scene understanding. However, segmentation-based convolutional neural networks require tremendous computational power. In this work, a fully-pipelined hardware accelerator with support for dilated convolution is introduced, which cuts down the redundant zero multiplications. Furthermore, we propose a genetic algorithm based automated channel pruning technique to jointly optimize computational complexity and model accuracy. Finally, hardware heuristics and an accurate model of the custom accelerator design enable a hardware-aware pruning framework. We achieve 2.44X lower latency with minimal degradation in semantic prediction quality (−1.98 pp lower mean intersection over union) compared to the baseline DeepLabV3+ model, evaluated on an Arria-10 FPGA. The binary files of the FPGA design, baseline and pruned models can be found in github.com/pierpaolomori/SemanticSegmentationFPGA

Leakage currents are one major concern when designing recent CMOS devices, making design for leakage at all stages of the design process mandatory. Early leakage optimization requires early leakage prediction, and for electronic system level design, this means estimation capabilities at register transfer (RT) level or above. Existing models are very accurate, but slow [transistor level such as Berkeley Simulator (BSIM)], or the slightly faster gate level models (such as the Liberty library), disregard relevant parameters. We present RT level leakage macro models, which are faster than recent gate level models, while preserving the accuracy of the transistor level models to a great extent. An estimation framework is proposed, describing the subthreshold, gate, and junction leakage of recent technology devices. The models are characterized using BSIM compact models and a Monte Carlo process variation description. Each varying BSIM parameter can be described. As an example of use, channel length, oxide thickness, and channel doping are regarded together with the temperature, supply voltage and body voltage. The final macro model needs less than a hundred parameters to capture the leakage behavior of an entire RT component and is still analytically describing the dependence to the process parameters. Compared to SPICE + BSIM, a model prediction is computed up to a hundred times faster for large RT components, and is, depending on the analyzed technology, within 2.1% (for 16-nm LP)-6.8% (for 65-nm bulk) deviation over a wide range of operating conditions and process variation settings.

The ever rising energy and accordingly cooling demands are a major hurdle for the scalability of today's supercomputers. We are challenged with the need to increase computation performance to cope with the rising complexity of calculations on the one hand and the need to keep the energy/cooling demand stable or in the best case even to reduce it. Recently, one widely discussed way to do this is the integration of heterogeneous computation devices into the supercomputer systems as these tend to have a far better performance/energy ratio for large classes of applications. The obvious drawback of heterogeneous systems is the additional design complexity for the software development in order to efficiently use these devices in terms of performance as well as power. For this reason we propose a flow, which assists the software developer at design time, offering immediate power- and performance-estimation. Such approaches are already known in the embedded world, helping there to select between different design possibilities, and will be used to get the best possible performance from a massively heterogeneous computation platform, while still keeping the energy consumption in mind.

The aging effect "Negative Bias Temperature Instability", which is highly dependent on device history, has a direct impact on the design of integrated circuits. In order to make realistic predictions available in the design process, simulation durations of existing history aware models must be significantly reduced. Therefore, a performance-oriented, yet accurate abstraction of the switching trap NBTI model is presented within this paper. Evaluation results for various stress scenarios demonstrate very precise NBTI simulations and a major improvement to another performance-oriented model abstraction. Simulation durations facilitate realistic aging predictions of larger components in a reasonable period of time.

We present a statistical life-time description for digital systems, which is characterised by short term functional simulation. Temperature and IR-drops for each hardware task of the system are regarded based on a coarse RT floorplan and a component wise prediction of the dynamic and leakage power. By iteratively updating threshold voltage and supply resistances, then dynamic and leakage power, then temperature and IR-drop distribution, electro-thermal coupling as well as long term degradation effects can be described.

In only 5 years, leakage developed from an academic corner phenomenon to a central problem of embedded system design. In sub 90nm designs the leakage power is already exceeding the dynamic power. The intention of this tutorial is to first review the mechanisms causing leakage and the parameters and imperfections causing leakage variation as the dependencies on physical parameters as temperature, voltage levels, device geometry, doping levels, etc. Afterwards, the state-of-the-art in leakage reduction and management methodologies is presented with a first focus on transistor design including well engineering, high-k, strained silicon, SGOI devices, fully depleted ultra thin body SOI, as well as FinFETs. Then, technical aspects on the leakage management techniques power gating, body and supply voltage scaling and minimum leakage vector are discussed. Finally, low leakage SRAM cell design and different cache decay techniques are presented.

Using our framework supporting simultaneous behavioral to RTL synthesis, component-wise floorplanning, as well as ABB (adaptive body biasing) and VDD aware power and delay prediction, we present a performance neutral methodology for optimal VDD-island generation and multiple ABB application. We show that tuning supply and body voltage for the entire design reduces the total energy dissipation by 4.6-38.1% without any performance loss. By allowing more than one body voltage and without optimizing the floorplan, the savings do not rise any further. Carefully floorplanning the design, we can additionally use VDD-islands reducing the power by 8.7-49.2%. In addition to the power savings, the power and delay variability due to PTV (process, temperature, voltage) variation can be reduced with all proposed ABB approaches, assuming that only the chip structure has to be fixed at design time, but the voltage levels can be adapted after the system manufacturing.

In this work we present a SPICE-based RTL subthreshold-leakage model analyzing components built in 70nm technology [1]. We present a separation approach regarding inter- and intra-die threshold variations, temperature, supply-voltage, and state dependence. The body-effect and differences between NMOS and PMOS introduce a leakage state dependence of one order of magnitude[2, 3]. We show that the leakage of RT-components still shows state dependencies between 20% and $80%. A leakage model not regarding the state can never be more accurate than this. The proposed state aware model has an average error of 6.7% for the RT-components analyzed.