In this paper, an iterative method is proposed for the optimization of wideband voltage-controlled oscillators (VCOs). The proposed method attempts to improve two significant performance metrics of wideband VCOs, i.e., the nonuniform band distribution and the nonconstant tuning gain KVCO. To address these nonideality issues, we introduce the deviation as a prior knowledge for calibration in each iteration step. The optimal capacitor array weighting plan can be asymptotically approached through multiple iterations. To demonstrate the efficacy of the proposed method, we use it to implement a 1-to-2.4-GHz LC-VCO and achieve a frequency tuning range of 82.4%. The optimized LC-tank involves 64 mixed cells, and each cell contains 2-bit binary-weighted switching capacitors, leading to 256 tuning bands. The LC-VCO with the synthesized tank achieves uniform frequency steps around 5 MHz with the relative error within ±4.4%. Meanwhile, the tuning gain KVCO is around 10 MHz/V with the relative error within ±3.2%. For this LC-VCO design, each iteration step costs about 55.9 s. After seven iterations, we approach the convergent solution where both the relative errors of the frequency steps and the tuning gains satisfy the given specifications.

Efficient performance modeling is an extremely important task for yield analysis and design optimization of analog circuits. In this paper, a novel regression modeling method based on hierarchical shrinkage priors is proposed to construct hybrid performance models with both high accuracy and low computational cost. In particular, the user-defined model templates derived from design equations and the general-purpose orthogonal polynomials are combined together to set up a hybrid dictionary. Next, in order to avoid over-shrinking large model coefficients, a novel regression method based on hierarchical shrinkage priors and variational Bayesian inference is adopted for model fitting. A rail-to-rail operational amplifier example demonstrates that the proposed method achieves up to 40% error reduction over other state-of-the-art approaches without increasing the modeling cost.

A fully differential charge pump is proposed in this paper. It adopts the replica technique to eliminate the effect of channel-length modulation, and the charging and discharging currents can match well in a wide output range. A rail-to-rail common-mode feedback circuit is employed to ensure the large swing of the charge pump unrestricted. The charge pump is designed and fabricated in SMIC 0.18μm CMOS process. The measured reference spur-level is about −73dBc and the in-band phase noise is nearly −90dBc/Hz@1KHz. The power dissipation of the charge pump is only 1mW.

New substrate isolation structures using pattern stacked pn junctions for on-chip inductors in standard CMOS technology are presented. For the first time, through increasing the reverse bias voltage to pn junctions, the lower substrate eddy loss due to the pn junction substrate isolation is reliably validated and the maximum quality factor is improved by 19%. The inductor without substrate shielding layer is compared to the inductor with metal one pattern ground shielding, pattern n-well, n+ diffusion, dual pn junctions isolation.

An accurate 1.08-GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process. In this paper we present a new convenient method of calculation of oscillating period. With this period calculation technique, the frequency tuning curves agree perfectly with the experiment. At a 3.3-V supply, the LC-VCO measures a phase noise of -82.2 dBc/Hz at a 10kHz frequency offset while dissipating 3.1mA current. Chip size is 0.86mm x 0.82mm.

This paper describes a new prediction method of tuning curves of a LC-tank voltage-controlled oscillator (VCO) with period calculation technique. With this period calculation technique, the prediction of oscillator tuning curves is more accurate compared with the traditional harmonic approximation. The theoretical analyses are experimentally validated with a CMOS complementary LC-tank VCO implemented in 0.35/spl mu/m 1P4M pure logic CMOS process.