Many emerging non-volatile memories are compatible with CMOS logic, potentially enabling their integration into a CPU’s die. This article investigates such monolithically integrated CPU–main memory chips. We exploit non-volatile memories employing 3D crosspoint subarrays, such as resistive RAM (ReRAM), and integrate them over the CPU’s last-level cache (LLC). The regular structure of cache arrays enables co-design of the LLC and ReRAM main memory for area efficiency. We also develop a streamlined LLC/main memory interface that employs a single shared internal interconnect for both the cache and main memory arrays, and uses a unified controller to service both LLC and main memory requests. We apply our monolithic design ideas to a many-core CPU by integrating 3D ReRAM over each core’s LLC slice. We find that co-design of the LLC and ReRAM saves 27% of the total LLC–main memory area at the expense of slight increases in delay and energy. The streamlined LLC/main memory interface saves an additional 12% in area. Our simulation results show monolithic integration of CPU and main memory improves performance by 5.3× and 1.7× over HBM2 DRAM for several graph and streaming kernels, respectively. It also reduces the memory system’s energy by 6.0× and 1.7×, respectively. Moreover, we show that the area savings of co-design permits the CPU to have 23% more cores and main memory, and that streamlining the LLC/main memory interface incurs a small 4% performance penalty.

3D Resistive Ram (ReRAM) technology exhibits the best attributes to suit present and emerging non-volatile memory storage applications. However, the major challenge to make ReRAM work in a 3D crossbar array is the integration of a selector device with a ReRAM device. The selector device will need to solve the so called “sneak path” barrier and enable large density memory arrays with low power consumption. Here, we report a Field Assisted Superlinear Threshold (FASTTM) Selector technology that overcomes the sneak path barrier with a selectivity ratio of 10E10. The switching and recover speed, on/off ratio, switching slope, program, erase, and read endurance, and variability of the FASTTMselector will be discussed. Prototype 1S1R devices with the FASTTM selector integrated with a low current ReRAM cell have been demonstrated and characterized. Figure 1 shows the representative I-V characteristics of a ReRAM cell with integrated FASTTMselector.