This paper presents a pathway toward realizing electronic skins with on-chip embedded slip detection through large-area thin-film transistor (TFT) technology with integrated capacitive shear sensors. It discusses end-to-end implementations optimized for TFT integration – from the sensor to the encoding of the slip. Enabled by the opportunities offered by an integrated solution, we envision next-generation slip sensors in prosthetics and robotics applications to achieve more human-like performance due to its higher sensing spatial resolution, reduced slip detection latency, lower system power consumption, thinner and more flexible form factor, improved ease of use, and lower cost. We propose to use a capacitive slip detection sensor integrated on a TFT substrate with embedded electronics. The paper describes and shows the results of the initial prototype of our proposed DERMIS system.

This work presents a VCO-based capacitance sensing circuit aimed at large area electrowetting on dielectric (EWOD) arrays in thin-film transistor (TFT) technology. The proposed solution can detect three levels of electrode capacitance (20fF/330fF/655fF) corresponding to three levels of droplet detection and can be implemented in-pixel (confined to the electrode’s area) or shared amongst several electrodes to enable higher resolution arrays. A method to perform calibrated measurements based on this circuit is demonstrated. Additionally, the pulsed nature of the proposed VCO’s output makes it resilient to large array parasitic elements during readout. An additional column-wise readout stage far from the electrode/pixel area is also proposed. This circuit’s total power consumption is 58.5μW and the area occupied is 418.2μm x 198.6μm including an EWOD electrode modeling capacitor.

This paper presents an automated approach for designing processors that support a subset of the RISC-V instruction set architecture (ISA) for a new class of applications at Extreme Edge.The electronics used in extreme edge applications must be area and power-efficient, but also provide additional qualities, such as low cost, conformability, comfort and sustainability.Flexible electronics, rather than silicon-based electronics, will be able to meet the above qualities.For this purpose, we propose a methodology for generating RISC-V instruction subset processors (RISSPs) tailored to these applications and implementing them as flexible integrated circuits (FlexICs).The methodology makes verification an integral part of the processor design by treating each instruction in the ISA as a discrete, fully functional, pre-verified hardware block.It automatically builds a custom processor by stitching together the instruction hardware blocks required by an application or a set of applications in a specific domain.We generate RISSPs using the proposed methodology for three extreme edge applications, and embedded applications from the Embench benchmark suite.When synthesized, RISSPs can achieve 8-to-43% reduction in area and 3-to-30% reduction in power compared to a processor supporting the full RISC-V ISA, and are also on average ~40 times more energy efficient than Serv -the world's smallest 32-bit RISC-V processor.When physically implemented as FlexICs, the three extreme edge RISSPs achieve up to 42% area and 21% power savings with respect to the full RISC-V processor.

An amplifier placed within a pixel is advantageous, as it offers gain at the first stage in the signal readout chain, but is limited by non-linearity. This paper presents a readout-circuit technique, that addresses the non-linearity issue of a current-mode pixel. The proposed circuit named ‘Pixel Follower’ compensates for the non-linearity by inverting it via feedback implemented locally. This avoids having to reduce the in-pixel amplifier gain, or sending any feedback signal to the pixel itself, thus greatly simplifying the design compared to other published techniques. The circuit has been manufactured in a Low Temperature Polycrystalline Silicon on foil process focusing on all LTPS-TFT large-area imager applications. The circuit operates at 5V supply and draws 200μW power with a total readout interval of 50μs. With a dynamic range of 2V on the pixel photo-diode voltage, the integral non-linearity is measured to be 2% outperforming the current state-of-the-art for large-area imagers.

This work elaborates on an amorphous Indium-Gallium-Zinc Oxide thin-film transistor model for a dual-gate self-aligned transistor configuration, enabling the design and realization of complex integrated circuits. The model originates from a mobility-enhanced transistor behavior model, whereby the additional backgate impacts key parameters, such as threshold voltage, mobility and subthreshold slope. The model has been validated for the full design flow and compared to measurement results, from single transistors, to inverters, ring oscillators and RFID transponder chips.

A detailed study of device characteristics and parameter variations of organic transistors on foil leads to the conclusion that design of p-type only digital circuits needs to focus on optimal yield, rather than on speed. From this perspective, subsequent generations of organic RFID tags have been realized, by increasing complexity (from 64 bit to 128 bit code generators), by adding functionality (Manchester encoding, anti-collision protocols), and by increasing data rate of the generated ID code (from 752 bits per second towards 50 kbit per second). As such, each of the requirements towards EPC compatible organic RFID tags is shown independently in code generators on foil, but not yet in a single RFID tag.