High-Speed digital-to-analog converters (DACs) are essential components in optical transmitters for global communication networks. As the demand for increased analog bandwidth grows, the commonly used, cost-effective CMOS technology is approaching its limitations. A promising solution is the interleaving of multiple DAC outputs through the nonlinear operation of an analog multiplexer (AMUX) in silicon-germanium technology. In this work, we present a behavioral model for 4:1 AMUX ICs, which reduces run times for system-level simulations by several orders of magnitude compared to layout-level IC simulations. We fit the model parameters using reference data from a 4:1 AMUX layout simulation while utilizing a stochastic algorithm to autonomously search the parameter space. The results show a close match of the reference data with the model output with low overfitting tendency, but also considerable variability in parameter influence on model accuracy.

Mixed-signal AI accelerators offer the possibility of higher energy efficiency for moderate resolution computations compared to their digital counterparts. All-analog implementations, where all operations are performed in the analog domain, can further improve this energy advantage. An energy efficient multiply-accumulate cell for all-analog neural layer processing macros is presented. The proposed analog two-quadrant multiplier circuit consists of two complementary MOSFETs where the pulse width modulated input activation is applied to the gates and the weight signal to the isolated back-gate. The analog multi-bit resolution weight is dynamically stored on a memory capacitor. The multiply-accumulate operation result is represented by charge accumulated on a summation line and drawn from or put onto a computation capacitance. Simulation results based on a 22 nm FD-SOI CMOS technology show that the cell consumes about 0.67 fJ for a circuit-level multiply-accumulate operation. An area efficiency of 166$\times$10$^{12}$MAC/s/mm$^2$is achieved.

In high-speed data transmission systems, CMOS digital-to-analog converters (DACs) at very high sampling rates are essential components allowing predistortion of the transmitted signal. Next to compensation of bandwidth limitations of the DAC and assembly, predistortion is also able to compensate other effects originating from time interleaving or from artifacts of the DAC circuit concept. Especially, linear, periodically time-varying (LPTV) effects are one source of impairments in the output signal causing spurious components and their compensation is of particular importance for time-interleaved systems. In this work, a universal predistortion concept including system identification based on the system’s reactions to unit impulses at all corresponding positions in a period is presented and applied to a 28-nm CMOS DAC with time interleaving by an analog multiplexer at sampling rates up to 100 GS/s. Measurements of this DAC reveal LPTV effects with a period of 32 affecting the analog output signal that may be attributed to time interleaving as well as architecture. A theoretical problem description is given and sources of LPTV distortions are identified. Starting from the theoretical description, a universal N:1 predistortion method in time domain is deduced based on a simple system identification method. Measurements of single-tone signals reveal a signal-to-noise and distortion ratio improvement up to 13.5 dB and around 7 dB for a broadband, two-level pulse-amplitude modulated signal at 100 GS/s compared to a linear, time-invariant filter. The proposed predistortion concept is a universal method to compensate for any N:1 LPTV artifacts with significant reduction of LPTV distortions and can be translated to a common transversal filter structure.

In this work, a mechanically flexible and high-speed transmitter front-end system is presented as a hybrid System-in-Foil (HySiF) by combining Chip-Film Patch (CFP) technology, a bow-tie dipole antenna, and cost-effective 0.25μm SiGe:C BiCMOS class-A mode power amplifier (PA) in a single compelling field. For the matter of a flexible system, the silicon (Si) chip is thinned down to 38 μm to be embedded into the polymer CFP carrier. For the sake of facilitating the thermal management of the die, an AlSiCu heat spreader is added underneath the thin silicon chip, thereby reducing the predicted temperature rise due to the self -heating loop inside the polymer. The measured gain center frequency of the PA with the ultra-thin silicon substrate shifts about 300 MHz towards higher frequencies due to the eddy current within the AlSiCu plate heat spreader at the backside of the chip. For that purpose, thermal behavior and RF performance of the system w.r.t. the different heat spreader structures are investigated. In addition, the pads of the embedded silicon chip are interconnected to the bow-tie dipole antenna by using a metal layer of AlSiCu through via openings on the foil.

Pulse shaping for signal transmission over bandwidth limited channels and for sensor systems is very important to control intersymbol interference and to comply with spectrum emission mask specifications by reducing the occupied bandwidth. In this work, an efficient, low-power concept for digital-to-waveform conversion is presented on a 22 nm CMOS node. A key characteristic is the approximation concept of a raised-cosine filter for waveform synthesis by non-binary weighting in the digital-to-analog converter (DAC) keeping hardware complexity and thus power consumption low. Due to the proposed pulse shaping method, spectral side lobes of a pseudo-random bit stream example can be reduced by more than 20 dB at 24 GS/s and a power consumption of only about 30 mW. In summary, this concept replaces high-resolution DACs or analog filters, respectively, in pulse shaping circuits by simple CMOS logic and an application-centric DAC.

Time-interleaving of energy-efficient data converter cores enables record symbol rates in electronic receivers. High-speed applications like optical data transmission or direct down-conversion in wireless mmWave receivers require ultra-high bandwidths and symbol rates, which CMOS data converters and especially their analog front ends cannot provide to date. We demonstrate a 64-GS/s track-and-hold circuit with a large-signal bandwidth of more than 61 GHz without any area-consuming peaking inductors, designed and manufactured in a 90-nm SiGe BiCMOS technology. The analog sampling front end exhibits a third harmonic distortion of -45 dBc to -32 dBc within the available frequency range of 50 GHz, which is better than the 5-bit requirement for 1.0-Vpp input signals. The ultra-high bandwidth of the circuit is twice as high as reported for CMOS data converters and in the range of broadband germanium photodiodes. This improves the bottleneck in hybrid integrated optoelectronic receiver front ends significantly. It is suited for time-interleaving of two channels with a doubled symbol rate of 128 GBaud, and the linearity allows to use it with 6-8-bit data converters.

This paper presents a CMOS switching mode amplifier in a 65 nm technology with 6 V output voltage swing. Due to the low breakdown voltage of the transistors, a stacked transistor topology is proposed. Thin-oxide FETs and thick-oxide FETs are used in the output stage to increase output power and reduce circuit complexity. Driven by a continuous-wave (CW) signal the amplifier can be operated up to 3 GHz. The two on-chip amplifier stages can be operated in differential mode. The measured broadband output power into 50 Ω is 21.3 dBm for 2 GHz and 18.5 dBm for 3 GHz in differential mode.

A digital bandpass delta-sigma modulator for class-S power amplifiers is presented. In comparison to a 2-level modulator coding efficiency can be increased by 10% over a large input power range with a 3-level modulator. Scaling the quantizer thresholds offers a trade-off between coding efficiency and signal-to-noise ratio. The bandpass modulator architecture allows twofold interleaving. A constraint on the quantizer thresholds and the feedback values reduces the effective operand word width in the feedback loop to the 5 most significant bits. Pipelining of the less significant bits leads to a short critical path. Interleaving and pipelining promise fast operation and thus a high maximum signal frequency.