This paper presents the system-level discussion, simulation design, and fabrication results of a novel analog ASIC - fabricated in 130nm BiCMOS technology - for interfacing resistive thermal sensors known as Fly Height Sensors (FHSs). FHSs are attached to the magnetic recording heads in modern hard disk drives (HDDs) to monitor the head-disk distance known as “fly height” by measuring the FHS resistance variation. The magnitude of the sensor signal serves as a measure of the proximity between the head and the disk surface which must accurately be controlled to minimize the fly height, thereby increasing the storage capacity of HDDs. The proposed interface includes two parts: 1) a dual-mode precise bias circuit that accurately provides a differential bias with a programmable common-mode voltage to the FHS in both voltage (V) and current (I) modes without requiring any calibrations, as well as featuring fast and smooth transient response, 2) front-end gain stages that create two separate signal paths with low- and high-frequency responses, called LF and HF blocks, utilized for controlling the fly height and mapping the roughness of the disk surface, respectively. The proposed bias circuit demonstrates high-impedance loading behavior on the sensor terminals in both V- and I- modes to have a unity signal gain at the sensor port and deliver it to the front-end amplifiers, resulting in an improvement of the overall noise performance of the interface. In addition, the bias noise power at the output of the LF block is suppressed to the extent of one order of magnitude thanks to deploying a noise cancellation technique. A low-noise and wide-bandwidth front-end is implemented for the HF block that eliminates the need for configuring the bias loop for having a low cutoff frequency, resulting in a reliable design with reduced complexity. Additionally, degenerated differential pairs with resistive loads, split tail currents, and Caprio’s quad offering low gain variation over the temperature and process are implemented as the front-end gain stages. The fabricated chip features an active area of 1.28 mm2with power consumption in the range of 110 to$172~mW$for the V-mode and 78 to$107~mW$for the I-mode, considering typical supply voltages of$+3.3\; V$and$-2.6 \;V$, and the sensor resistance ($R_{SNS} = 75\; \Omega $) and the sensor current ($I_{SNS}$) from 0.5 to$6\;mA$.

Evolution in consumer electronics has brought the need for high-current laser diode drivers (LDDs) compatible with integrated systems on chip (SOCs). Traditional solutions device-based are migrating to integrated architectures granting easy digital control, compliance to the voltage rails and fast switching times. The introduction of the digital control directly implies the need of digital-to-analog converter (DAC) structures for the modulation of the laser current and the chosen solution has to match the analog performances required for the particular application. This paper presents a current-mode DAC architecture for LDDs together with a 9-bit implementation which targets a rise time of 1.5 ns for a zero-to-full-current (51 mA) switching condition. A 0.105-mm2prototype has been manufactured in a 130-nm BiCMOS technology, and the experimental measurements are reported.

Advanced communication systems, smart and biomedical technologies have led to the need of complex laser systems. The traditional solutions, inherited by the traditional optical communication architectures, start to present limitations due to the high output compliance and high power consumption. Moreover, the common anode topologies present scarce adaptability to multi-purpose systems implemented in present systems on chip. This paper presents and discusses DAC architectures for a common cathode current driver suitable for laser system applications. The discussion is supported and complemented by results collected from simulations at the transistor level using a 0.13-μm BiCMOS technology.

As data rates required for systems in package (SiPs) increase and their complexity increases, signal integrity issues become increasingly difficult to address. The design flow of the SiP should therefore take into account these issues from the beginning. A design flow aimed at designing the SiP tracks is presented; its suitability for the design of packages comprising multiple stacked memories is verified through a design example. The proposed flow for signal integrity can be integrated easily within the complete design of the SiP.