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Xueqing Lu

dblp:63/10803 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
delay-locked loop		 0.112012
A low power and small area all digital delay-locked loop based on ring oscillator architecture · Sci. China Inf. Sci. 2012
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design		 0.112012
A low power and small area all digital delay-locked loop based on ring oscillator architecture · Sci. China Inf. Sci. 2012
Integrated circuit design
low-power circuit design		 0.012012
A low power and small area all digital delay-locked loop based on ring oscillator architecture · Sci. China Inf. Sci. 2012
YearPublicationVenuePosition
2012 A low power and small area all digital delay-locked loop based on ring oscillator architecture
Jiapeng Zheng, Xueqing Lu, Yangyuan Wang
 Sci. China Inf. Sci.3