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Herbert De Smet

dblp:63/1413 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2012
0000-0001-9640-8454ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Graphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
boundary element method		 0.011993
A 2-D boundary element method approach to the simulation of DMOS transistors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Electronic design automation › technology computer-aided design
device simulation		 0.011993
A 2-D boundary element method approach to the simulation of DMOS transistors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Electronic design automation › technology computer-aided design
semiconductor device simulation		 0.011993
A 2-D boundary element method approach to the simulation of DMOS transistors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993

Methods — techniques the papers use, named apart from their topics

finite difference method · 0.0boundary element method · 0.0
YearPublicationVenuePosition
2012 Efficient disparity vector prediction schemes with modified P frame for 2D camera arrays
Aykut Avci, Jan De Cock, Peter Lambert, Roel Beernaert, Jelle De Smet, Lawrence Bogaert, Youri Meuret, Hugo Thienpont, Herbert De Smet
 J. Vis. Commun. Image Represent.9
1993 A 2-D boundary element method approach to the simulation of DMOS transistors
abstract
A boundary element method is introduced for the calculation of two-dimensional potential and electric field distributions in high-voltage DMOS transistors. An algorithm is proposed to determine the dimensions of the depletion layers in two-dimensional geometries. Regions with different permittivities are taken into account using appropriate boundary conditions. As an application, the high-voltage behavior of the DMOS transistors is investigated, and the avalanche breakdown conditions of the transistors are determined by calculating the ionization integral. The results are compared with simulations based on finite difference methods.>
Ming-Jiang Zhou, Herbert De Smet, Anita De Bruycker, André Van Calster
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2