Multi-label text classification (MLTC) tasks in the medical domain often face the longtail label distribution problem.Prior works have explored hierarchical label structures to find relevant information for few-shot classes, but mostly neglected to incorporate external knowledge from medical guidelines.This paper presents DKEC, Domain Knowledge Enhanced Classification for diagnosis prediction with two innovations: (1) automated construction of heterogeneous knowledge graphs from external sources to capture semantic relations among diverse medical entities, (2) incorporating the heterogeneous knowledge graphs in few-shot classification using a label-wise attention mechanism.We construct DKEC using three online medical knowledge sources and evaluate it on a real-world Emergency Medical Services (EMS) dataset and a public electronic health record (EHR) dataset.Results show that DKEC outperforms the state-of-the-art labelwise attention networks and transformer models of different sizes, particularly for the fewshot classes.More importantly, it helps the smaller language models achieve comparable performance to large language models.

Emergency Medical Services (EMS) providers use their hands extensively for the rescue operation and providing care to the patients in an EMS scene. Using smartwatch based sensor data, i.e., accelerometer, gyroscope, and magnetometer, we are developing SenseEMS, a system for hand operated EMS intervention detection and real-time monitoring. SenseEMS will use a hybrid deep neural network with appropriate real-time algorithms on the sensor data to detect multiple hand operated activities, i.e. CPR compressions, attaching defibrillation pads and breathing bags, and to provide quality assessment on different metrics of the activity, i.e., the rate and depth of CPR compressions. Our initial results for this ongoing research show promising accuracy. Preliminary survey with 31 anonymous EMS responders suggests that this automated system will be highly beneficial for real-scene application and EMS training.

Commercial virtual-desktop computing is well established using computers optimized to serve as thin clients connected to centralized computing systems. Some common residential applications impose more stringent requirements on both communication bandwidth and latency than those of typical commercial applications. This article describes an objective study of residential applications accessed through thin-client virtual desktops for the purpose of investigating the feasibility of applying virtual-desktop computing to residential users. New metrics are introduced to quantify user-received application performance. The results suggest that certain commercial solutions with a commodity datacenter server show a strong potential for being adapted to residential virtual-desktop computing.

EMS (emergency medical service) plays an important role in saving lives in emergency and accident situations. When first responders, including EMS providers and firefighters, arrive at an incident, they communicate with the patients (if conscious), family members and other witnesses, other first responders, and the command center. The first responders utilize a microphone and headset to support these communications. After the incident, the first responders are required to document the incident by filling out a form. Today, this is performed manually. Manual documentation of patient summary report is time-consuming, tedious, and error-prone. We have addressed these form filling problems by transcribing the audio from the scene, identifying the relevant information from all the conversations, and automatically filling out the form. Informal survey of first responders indicate that this application would be exceedingly helpful to them. Results show that we can fill out a model summary report form with an F1 score as high as 94%, 78%, 96%, and 83% when the data is noise-free audio, noisy audio, noise-free textual narratives, and noisy textual narratives, respectively.

IMACS is an intelligent, interactive cognitive assistant dedicated to cardiac arrest cases in Emergency Medical Service (EMS). EMS providers deal with many cardiac cases. IMACS interacts with EMS providers in real-time and collects vital information from the providers' conversation, including names of interventions, timestamps of interventions, and dosage amount. Throughout the process, IMACS provides necessary reminders and creates a summary report afterward. Using the dynamic behavioral model of two different cardiac arrest recovery protocols, we have developed a critical risk-index based approach to provide time-sensitive feedback and suggest alternatives to the providers in real-time. Our experiments reveal an F1-score of 83% with 300 test cases. A qualitative study also reflects that seven out of ten of the EMS providers rate the system as very helpful in correctly executing cardiac arrest EMS protocols.

This paper presents a cognitive assistant system for emergency medical services (EMS) that can serve as a rescue robot or virtual assistant, helping with improving situational awareness of the first responders through automated collection and analysis of data from the incident scene and providing suggestions to them. The proposed system relies on a Behavior Tree (BT) framework that combines the knowledge of EMS protocol guidelines with speech recognition, natural language processing, and machine learning methods to (i) extract critical information from responders' conversations and verbalized observations, (ii) infer the incident context, and (iii) decide on safe and effective response interventions to perform. We use a data-set of 8302 real EMS call records from an urban, high volume regional ambulance agency in the U.S. to evaluate the responsiveness and cognitive ability of the system and assess the safety of the suggestions provided to the responders. The experimental results show that the developed cognitive assistant achieves an average top-3 accuracy of 89% in selecting the correct EMS protocols and an average F1-score of 71% in suggesting the protocol specific interventions while providing transparency and evidence for the suggestions.

Fault injection methods have long been used to assess fault tolerance and safety. However, many conventional fault injection methods face significant shortcomings, which hinder their ability to execute fault injections on target real-time safety-critical systems. We demonstrate a novel fault injection system implemented on a commercial Field-Programmable Gate Array board. The fault injector is unobtrusive to the target system as it utilizes only standardized On-Chip-Debugger (OCD) interfaces present on most current processors. This effort resulted in faults being injected orders of magnitude faster than by utilizing a commercial OCD debugger, while incorporating novel features such as concurrent injection of faults into distinct target processors. The effectiveness of this high performance fault injector was successfully demonstrated on a tightly synchronized commercial real-time safety-critical system used in nuclear power applications.

The GOAL (Guided On-Demand Adaptive Learning) project produced three computer-based instruction modules for use in a course on Digital Logic Design. GOAL modules teach concepts interactively, provide exploratory interactive activities, and present material in a style that best matches the student's preferences. In addition, GOAL allows the student to set the pace, providing more detail and explanation when needed, moving quickly when possible. GOAL also can evaluate knowledge through assessment activities, allowing a student to earn validated credits for demonstrated mastery of material. Evaluation of the data collected during three semesters of student trials suggest that students using GOAL can achieve comparable learning in significantly less time. than traditional classroom lectures.

Existing nuclear power generation facilities are currently seeking to replace obsolete analog Instrumentation and Control (I&C) systems with contemporary digital and processor based systems. However, as new technology is introduced into existing and new plants, it becomes vital to assess the impact of that technology on plant safety. From a regulatory point of view, the introduction or consideration of new digital I&C systems into nuclear power plants raises concerns regarding the possibility that the fielding of these I&C systems may introduce unknown or unanticipated failure modes. In this paper, we present a fault injection based safety assessment methodology that was applied to a commercial safety grade digital Reactor Protection System. Approximately 10,000 fault injections were applied to the system. This paper presents a overview of the research effort, lessons learned, and the results of the endeavor.

There are several attacks that exploit the presence of side channels in hardware implementations of cryptographic algorithms to extract secret data. Differential power analysis (DPA) and simple power analysis (SPA) attacks sense the power consumption of the hardware to extract the secret cryptographic key. These attacks either directly examine the power traces or carry out statistical operations on the power traces obtained from the hardware while executing the cryptographic algorithm. This paper presents a circuit that can be added to crypto-hardware to suppress information leakage through the power supply pin side channel. We discuss the design, simulation results and the limitations of the suppression circuit. We show that this countermeasure significantly increases the number of power trace samples required to undertake a DPA attack. The countermeasure does not require any assumptions about the design of the hardware under protection.

The basic question addressed was whether the greater hardware utilization offered by reconfigurable functional units could compensate for a reduction in clock rate. That is, would the average number of clock cycles per instruction improve sufficiently to compensate for a slower clock rate to yield a net improvement in performance? The architecture limited the number of execution units because of constraints external to the execution units. An example of such a constraint would be limited efficient access to a common register file. Under these constraints, inefficient matching of program needs with hardware capabilities limits performance because of hardware idle cycles. The work found very limited conditions that can yield performance improvement using reconfigurable pipelines when compared with static pipelines. Greater promise was found with instruction set enhancements made possible by the reconfigurable pipelines.

The design of complex systems requires an enormous amount of modeling and simulation at the various levels of detail to assure high quality results. Most design methodologies require the use of separate modeling languages and simulation environments for each refinement step and simulation technique. Since one of the major goals of design is to reduce the time to market for a given system, the current approaches are becoming unacceptable. A new unified modeling (UM) methodology is under development at the University of Virginia which provides a top-down/bottom-up design methodology based on a single modeling environment. This single environment methodology is made possible through a technique known as hybrid modeling, which enable the simulation and analysis of behavioral components within a system-level model. By simulating behavioral components along with components at the system modeling level, high risk portions of the design can be examined at earlier stages in a given product's development; thus reducing the time to market. The paper examines the hybrid modeling techniques which make this multi-level modeling possible.

Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Parallel processing techniques can be applied to accelerate the process of finding test patterns. One problem with this approach is that most currently available distributed memory multicomputers have a limited amount of memory on each processor which limits the size of the circuit database that can be contained on a single node. Topological partitioning of the circuit database across several processors can increase the size of VLSI circuits that can be processed on a given parallel machine. This paper presents the architecture of a topologically partitioned ATPG system and several partitioning algorithms that can be used to partition the circuit-under-test. This paper also presents several parallelization methods that may be applied to topologically partitioned ATPG on a distributed memory multicomputer. Results of using these parallelization techniques along with topological partitioning are presented.>

There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The single path design methodology presented is a possible solution to this problem. The basic concept of the methodology is the use of one simulation language, the VHSIC hardware description language (VHDL, Version 1076) for all phases of design. The VHDL framework allows for iterative stepwise refinement of a model. A performance (uninterpreted) model can be refined to a register transfer level (RTL) description without changing modeling environments or completely rewriting the models. As an example, the performance-modeling phase of the single path design methodology is applied to the WM machine, a superscalar computer architecture.>

The conversational constraints of text-to-speech synthesis systems are considered by permitting the human user to control the motions of stimulated articulators in a synthesized vocal track. The positions of these stimulated articulators are used to derive parameters to control a formant synthesizer. It is anticipated that use of this type of speech prosthesis will be more difficult to learn than the use of conventional communication aids, but the flexibility of this approach will be much greater. The difficulty in this approach arises because the complexity of the human interface must be limited while sufficient information must be obtained to permit synthesis of speech sounds at conversational rates. A prototype has been constructed, and experimentation and further development are discussed.>

An investigation is presented of an extension, proposed by A.A. Minai and R.D. Williams (Proc. Int. Joint Conf. on Neural Networks, vol.1, p.676-79, Washington, DC, 1990), to an algorithm for training neural networks in real-valued, continuous approximation domains. Specifically, the most effective aspects of the proposed extension are isolated. It is found that while momentum is particularly useful for the delta-bar-delta algorithm, it cannot be used conveniently because of sensitivity considerations. It is also demonstrated that by using more subtle versions of the algorithm, the advantages of momentum can be retained without any significant drawbacks

Article Tailor: creating custom user interfaces based on gesture Share on Authors: Randy Pausch University of Virginia, Thornton Hall, Charlottesville, VA University of Virginia, Thornton Hall, Charlottesville, VAView Profile , Ronald D. Williams University of Virginia, Thornton Hall, Charlottesville, VA University of Virginia, Thornton Hall, Charlottesville, VAView Profile Authors Info & Claims UIST '90: Proceedings of the 3rd annual ACM SIGGRAPH symposium on User interface software and technologyAugust 1990 Pages 123–134https://doi.org/10.1145/97924.97939Online:01 August 1990Publication History 11citation671DownloadsMetricsTotal Citations11Total Downloads671Last 12 Months41Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

An automated system for creating and managing VHDL design units is described in this paper. This system helps the hardware designer to learn the syntax of the VHSIC Hardware Description Language (VHDL) and to produce code which can be used for simulations. This demonstration prototype tool is written in C to run on a Sun workstation, and it produces IEEE standard 1076 VHDL code.

The authors discuss methodologies and tools that allow a system to be analyzed using Petri nets or queuing models. Models at this level contain tokens rather than values, and the function of blocks remains undefined. Such analysis is performed early in the design process to evaluate overall system performance. Different methodologies and tools are available to allow design analysis and verification at interpreted levels through hardware design language (HDL) descriptions. Tokens are replaced with specific values for the representation of signals. The methodology presented allows the designer to create uninterpreted models in an environment already capable of interpreted modeling, the VHSIC hardware description language (VHDL). Uninterpreted modeling in an HDL is the first step in the creation of a continuous single-path design environment.>

The significant computational requirements of VLSI layout suggest that it may be desirable to estimate the feasibility of a task before actually performing the task. The system described in this paper uses a discrete heuristics approach to estimate the future quality of a semi-custom layout before any placement or routing is done. It does this evaluation with respect to critical parameters such as routability, area utilization, and wire length, using heuristics arranged in a discrete graph structure. The system can handle user-specified non-rectangular layout shapes. Its rule-based structure allows easy observation and modification of individual heuristics for the purposes of “fine tuning.” The system also detects potential problems and suggests possible solutions.

The allocation of resources to competing entities is a significant problem in various applications areas. There are many examples of situations in which it is necessary to impose a global constraint limiting the total quantities of resources available to individual consumers while there is no global objective to govern the distribution. The problem of limiting peak demand for power among loosely related buildings such as those on a college campus provides an example application. The individual objective performances of some loosely coupled independent buildings can be improved if resources can be exchanged, but such exchange becomes difficult if resource exchanges are required to balance. Since the buildings are independent, the exchange of resources may be required to occur without compromising this independence. A mechanism is presented to support resource exchanges among independent users while assuring that the average resource exchanged remains at zero and the autonomy of the individual users is retained. The presented mechanism uses a simplified form of barter to eliminate the need for gaming in certain cases.