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Sung Chung

dblp:63/3 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › design for testability
built-in self-test		 0.012002
Embedded test control schemes for compression in SOCs · DAC 2002
Electronic design automation › hardware verification and test › system-on-chip testing
embedded core testing		 0.012002
Embedded test control schemes for compression in SOCs · DAC 2002
Electronic design automation
hardware verification and test		 0.012002
Embedded test control schemes for compression in SOCs · DAC 2002
YearPublicationVenuePosition
2005 A Power-Aware Branch Predictor by Accessing the BTB Selectively
Cheol Kim, Sung Chung, Chu Shik Jhon
 J. Comput. Sci. Technol.2
2002 Embedded test control schemes for compression in SOCs
abstract
This paper presents novel control schemes for testing embedded cores in a system on a chip (SOC). It converts a traditional BIST scheme into an externally controllable scheme to achieve a high test quality within optimal test execution time without inserting test points. The scheme promotes design and test reuse without revealing IP information.
Douglas Kay, Sung Chung, Samiha Mourad
 DAC2