This paper presents two computer architecture mechanisms that can be employed together to allow programs to be written where their individual instructions can (1) be executed in parallel in separate processors and (2) be arbitrarily assigned to be executed by any processor in a connected fabric of processors. This is an emerging parallel execution technique for future high performance and embedded computers. Changing the placement of a program's instructions in a processing fabric is equivalent to rearranging the computer architecture around the program itself. Reasons to change the computer architecture around the software are to improve overall execution speed and to perform load balancing. The two computer architecture mechanisms are (1) a custom dataflow instruction set and (2) a processor block called an operation cell. The most important feature of the instruction set is the high level of operational independence of the instructions (i.e. no shared memory/registers between instructions). The operation cell is a processor construct that stores an instruction and manages the execution life of that instruction. An operation cell either executes the instruction itself or forwards the execution to another operation cell in a different processor.

A dataflow processor is presented that is to be used as the basis of a tiled polymorphic computing architecture. The key contribution is a new scheme that allows a program's instructions to be migrated before and during runtime in a fine-grained manner across the collection of processors. The primary reason to perform this migration is to execute programs faster. Other reasons to perform instruction migration are to prioritize computational resources and to achieve thermal balancing. The act of performing instruction migration across of a collection of processors is logically equivalent to rearranging the computer architecture under the program (i.e., polymorphic computing). Additionally, a new dataflow instruction set which enables the migration is presented. This instruction set is built upon the concept of a single RISC-like dataflow instruction that can atomically execute, make decisions, and independently route results. Furthermore, the novel concept of an operation cell is presented. An operation cell holds a single instruction and its data. It also contains logic to independently determine when an instruction is executed and when to forward data to other operation cells in the collection of processors. In addition, the internal architecture of this processor is presented. This includes the arithmetic logic unit (ALU) that is used to execute the instructions and a series of buses that allow data movement to occur in parallel to instruction execution. Finally, an inter-processor migration strategy is defined.

In this paper, a new pipelined, reduced memory CORDIC-based architecture is presented for any radix size FFT. A multi-bank memory structure and the corresponding addressing scheme are used to realize the parallel and in-place data accesses. The proposed memory-reduced CORDIC algorithm eliminates the need for storing twiddle factors and angles, resulting in significant area savings with no negative impact on performance. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthesis results match the theoretical analysis and it can be observed that more than 20% reduction can be achieved in total memory logic.

In various signal processing applications, decomposition and analysis of non-stationary signals is a challenging problem. In this work, we present a computationally efficient method, fast chirplet signal decomposition (FCSD) algorithm, for decomposing highly convoluted signals into a linear expansion of chirplets, and successively estimates the chirplet parameters. These parameters are capable of representing a broad range of echo shapes, including the broad-band, narrow-band, symmetric, skewed, nondispersive or dispersive, and have significant physical interpretations for radar, sonar, and ultrasonic imaging applications. For the real-time implementation of chirplet signal decomposition algorithm, an FPGA-based hardware/software co-design is developed on Xilinx Virtex II Pro FPGA platform. In this study, based on the balance among the system constraints, cost, and the efficiency of estimations, the performance of different algorithm implementation schemes have been explored. The developed system successfully exhibits the robustness in the chirplet signal decomposition of experimental signals. This type of study addresses a broad range of applications including velocity measurement, target detection, deconvolution, object classification, data compression, and pattern recognition.

This paper studies an adder technique that performs three input addition utilizing parallel prefix adders. The adder architectures are called three-input flagged prefix adders (TIFPA) due to the utilization of a new set of intermediate outputs called flag bits to obtain the desired result. One of the advantages of this technique is the elimination of dedicated adder units to perform three-input addition. This adder can find its use in applications such as multiplication or multi-media units. This paper examines the effect on the performance of the adder when the operand size is expanded from 16 bits to 32 and 64 bits. Furthermore, a logical effort analysis has also been performed on the TIFPA to confirm the simulation and analytical results. The performance of this adder design has been compared to that of carry save adders (CSA) to understand the performance gain of the proposed technique. The comparison has been made with respect to the simulation results and also on the basis of logical effort.

This letter presents a fast chirplet transform (FCT) algorithm, a computationally efficient method, for decomposing highly convoluted signals into a linear expansion of chirplets. The FCT algorithm successively estimates the chirplet parameters in order to represent a broad range of chirplet shapes, including the broadband, narrowband, symmetric, skewed, nondispersive, or dispersive. These parameters have significant physical interpretations for radar, sonar, seismic, and ultrasonic applications. For the real-time application and embedded implementation of the FCT algorithm, an FPGA-based hardware/software co-design is developed on Xilinx Virtex-II Pro FPGA development platform. Based on the balance among the system constraints, cost, and the efficiency of estimations, the performance of different algorithm implementation schemes have been explored. The developed system-on-chip successfully exhibits robustness in the chirplet transform of experimental signals. The FCT algorithm addresses a broad range of applications including velocity measurement, target detection, deconvolution, object classification, data compression, and pattern recognition.

For multi-operand addition, several techniques, such as carry-save adders, Wallace, and Dadda structures based on counters and compressors have been proposed. This paper proposes a technique to accomplish three-operand addition utilizing regular adder structures such as parallel-prefix adders. One of the advantages of this technique is the elimination of dedicated adder units to perform three-input addition. Conventional prefix adders are modified to generate intermediate outputs called flag bits to allow the addition of a third arbitrary number, thereby accomplishing multi-operand addition. This adder can find its use in applications such as multiplication or multi-media units. An evaluation has been performed for 16-bit three-input flagged prefix adder architectures (TIFPA) in terms of area, delay and power. The performance of this adder design has been compared to that of carry save adders to understand the performance gain of the proposed technique.

The decimal arithmetic has been receiving an increased attention because of the growth of financial and scientific applications requiring high precision and increased computing power. This paper presents an efficient architecture for multi-digit decimal addition based on carry-free signed-digit numbers. In this study, the decimal adder architecture has been designed and synthesized using the TSMC 0.18μ technology. The synthesis results were compared to the existing decimal adders with respect to design area, delay and power consumption. These results show that proposed adder architecture improves the area-delay factor by 3 for a 32 digit adder.

We present a reconfigurable ultrasonic processor which can simultaneously employ two different ultrasonic imaging applications: ultrasonic target detection and signal compression. The underlying hardware design makes use of the fact that both applications share the same algorithm fundamentals. A unified architecture implements signal decomposition and reconstruction with forward and inverse DCT and DWT. After the forward transform step, a thresholding operation is applied to discriminate either frequency bands for target detection or coefficient amplitudes for data compression. The flexibility and the modular design make this reconfigurable architecture an effective and practical solution for real-time ultrasonic imaging applications.