Analog in-Memory Computing (AiMC) based on Phase-change Memory (PCM) enables highly efficient Ma-trix-vector Multiplication (MVM) for edge-AI workloads. However, sequential programming of PCM cells introduces timedependent conductance misalignments that may degrade computational accuracy, especially in large arrays. This work analyzes the impact of programming delay-induced errors in PCM-based AiMC systems. An analytical model is derived to characterize the resulting MVM error as a function of array size, programming time, and drift coefficients. Then, two mitigation techniques are proposed to mitigate the MVM error, namely Importance-Aware Scheduling (IAS) and Digital Rescale Compensation (DRC). These approaches are experimentally validated on a 512×512 PCM-based AiMC prototype, achieving up to 85% reduction of MVM error induced by the programming scheme.

This paper presents a Threshold Voltage Generator (TVG) for IoE receivers featuring ULP comparators (CMPs). Prior art TVGs dynamically generate the CMP threshold to enable the receiver to process time-varying received power. However, they require a large area and additional circuits to ensure that the IoE system operates with minimal energy consumption regardless of temperature changes. The proposed TVG has been implemented in a 90-nm STMicroelectronics CMOS technology with a 0.6-V supply, targeting 1-kbps datarate. It occupies 40x less area than RC-based TVGs, consumes 2.2 nA and ensures a 3.5-dB SNR boost without affecting IoE system performances. When compared to previous art, it allows for a 10x energy consumption reduction without requiring any additional circuits. Monte Carlo simulations of an ULP receiver equipped with the proposed TVG show a 0-% Packet Error Rate from -40 °C to +85 °C.

A Threshold Voltage Generator (TVG) circuit for continuous-time comparators is presented. It may be used in ULP IoT systems requiring nanoWatt power consumption, kbps bitrates and the reception of packets with lengths up to hundreds of bits. The circuit is based on a switched capacitor technique to generate the threshold voltage without requiring any large area resistors and with the system clock active only during the reception of data, thus minimizing energy consumption. Latency is also minimized as the threshold is generated within the first received bit of the packet. The reception of packets with no limits on their length is made possible by continuously updating the threshold, which also allows correct operation even in case of amplitude variations in the incoming signal during the data reception. It has been implemented and verified through post-layout simulations in an STMicroelectronics 90-nm CMOS technology with a 0.6-V supply, targeting a 1-kbps bitrate. It occupies an area lower than 0.001 mm2, which is less than 1% of the area of a standard RC-based TVG implemented in the same technology. A prototype of the proposed TVG is currently under fabrication.

The search for energy efficient circuital implementations of neural networks has led to the exploration of phase-change memory (PCM) devices as their synaptic element, with the advantage of compact size and compatibility with CMOS fabrication technologies. In this work, we describe a methodology that, starting from measurements performed on a set of real PCM devices, enables the training of a neural network. The core of the procedure is the creation of a computational model, sufficiently general to include the effect of unwanted non-idealities, such as the voltage dependence of the conductances and the presence of surrounding circuitry. Results show that, depending on the task at hand, a different level of accuracy is required in the PCM model applied at train-time to match the performance of a traditional, reference network. Moreover, the trained networks are robust to the perturbation of the weight values, up to 10% standard deviation, with performance losses within 3.5% for the accuracy in the classification task being considered and an increase of the regression RMS error by 0.014 in a second task. The considered perturbation is compatible with the performance of state-of-the-art PCM programming techniques.

Several recent works have shown the advantages of using phase-change memory (PCM) in developing brain-inspired computing approaches. In particular, PCM cells have been applied to the direct computation of matrix-vector multiplications in the analog domain. However, the intrinsic nonlinearity of these cells with respect to the applied voltage is detrimental. In this paper we consider a PCM array as the encoder in a Compressed Sensing (CS) acquisition system, and investigate the effect of the non-linearity of the cells. We introduce a CS decoding strategy that is able to compensate for PCM nonlinearities by means of an iterative approach. At each step, the current signal estimate is used to approximate the average behaviour of the PCM cells used in the encoder. Monte Carlo simulations relying on a PCM model extracted from an STMicrolectronics 90 nm BCD chip validate the performance of the algorithm with various degrees of nonlinearities, showing up to 35 dB increase in median performance as compared to standard decoding procedures.

Internet of Things (IoTs)-based monitoring applications usually involve large-scale deployments of battery-enabled sensor nodes providing measurements at regular intervals. In order to guarantee the service continuity over time, the energy-efficiency of the networked system should be maximized. In this paper, we address such issue via a combination of novel hardware/software solutions including new classes of Wake-up radio IoT Nodes (WuNs) and novel data- and hardware-driven network management algorithms. Three main contributions are provided. First, we present the design and prototype implementation of WuN nodes able to support two different energy-saving modes; such modes can be configured via software, and hence dynamically tuned. Second, we show by experimental measurements that the optimal policy strictly depends on the application requirements. Third, we move from the node design to the network design, and we devise proper orchestration algorithms which select both the optimal set of WuN to wake-up and the proper energy-saving mode for each WuN, so that the application lifetime is maximized, while the redundancy of correlated measurements is minimized. The proposed solutions are extensively evaluated via OMNeT++ simulations under different IoT scenarios and requirements of the monitoring applications.

This paper presents a power-aware scheduling algorithm based on efficient distribution of the computing workload to the resources on heterogeneous CPU-GPU architectures. The scheduler manages the resources of several computing nodes with a view to reducing the peak power. The algorithm can be used in concert with adjustable power state software services in order to further reduce the computing cost during high demand periods. Although our study relies on GPU workloads, the approach can be extended to other heterogeneous computer architectures. The algorithm has been implemented in a real CPU-GPU heterogeneous system. Experiments prove that the approach presented reduces peak power by 10 percent compared to a system without any power-aware policy and by up to 24 percent with respect to the worst case scenario with an execution time increase in the range of 2 percent. This leads to a reduction in the system and service costs.

Embedded field programmable gate arrays (eFPGA) can provide modern systems-on-a-chip (SoCs) with the flexibility required to face the growth of nonrecurring engineering and manufacturing costs. On the other hand, SoC designers usually perceive eFPGAs as area-hungry IPs with poor flexibility in terms of performance, power and area tradeoff since they are typically available as custom-designed hard macros. In this scenario, technology scaling is allowing designers to reduce the impact of the eFPGA area gap, while effective exploitation of all the technology options (e.g., the transistor threshold) entails moving toward soft-core eFPGAs to match specific application needs. In this paper, we propose an look-up table-based soft-core eFPGA featuring a synthesizable and parametric architecture. A key point of our proposal is that we have adopted a multistage switching network (MSSN) to implement the programmable interconnect, since this ensures a synthesizable and congestion-free architecture. Quantitative evaluation of our eFPGA shows a significantly wide design-space available on very different technologies (we experimented STMicroelectronics CMOS 65 nm and BCD9s 0.11 μm). Application-driven evaluation showed how for a fixed eFPGA size (i.e., number of logic blocks) different configurations of the MSSN allow designers to speed up performance by 20/60%, as well as to maximize the computational density for a given area budget.

Non-contact probing can provide an important contribution for testing complex Systems-on-a-Chip (SoC), Systems-in-a-Package (SiP) and Through-Silicon-Vias (TSV) interconnections. This paper demonstrates the feasibility of wireless testing by capacitive coupling between a cantilever probe card and a pad. In particular a scheme of an I/O pad suitable for both contact and contactless probing is proposed.

3D chip-to-chip capacitive interconnections are in common practice characterized with FEM solvers as they cannot be modeled as lumped RLC circuits as ohmic 3D interconnects. This paper describes some drawbacks of this procedure and proposes an innovative flow, based on post-layout parasitic extraction tools, to enable the designer to place capacitive interconnects as constrained macros in a digital design flow.

In this paper, a silicon compiler for analog fuzzy controllers is described. The layout is generated automatically, starting from global-system specifications accepted as a set of classical fuzzy rules involving fuzzy sets as well as numerical data, often available from numerical examples. The system relies on a library of basic cells designed using a CMOS n-well 0.7 /spl mu/m technology and on the use of Cadence software. Multi-inputs multi-outputs fuzzy logic-based controllers are synthesized, and the area and power requirements by any specific application are optimized. Some prototypes designed using the proposed methodology have been fabricated. For example, a two-inputs two-outputs fuzzy controller implementing a 2D rational function and a sinusoidal function requires, including the I/O circuitry, 1.9 mm/sup 2/ of silicon area, and the total power consumption is 44 mW at 5 V power supply. The maximum propagation delay, assuming a step input function, is 0.57 /spl mu/sec. The total computation time using a SUN Sparc2 Workstation is about 25 min, from specification of the expected behavior to layout.