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P. Barri

dblp:63/3581 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Internet architecture and protocols · 50% Routing and switching · 50%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet architecture and protocols › ATM networks
ATM switching
0.011991
Implementation of a 16 to 16 Switching Element for ATM Exchanges · IEEE J. Sel. Areas Commun. 1991
Integrated circuit design › semiconductor technology › semiconductor process technology
BiCMOS technology
0.011991
Implementation of a 16 to 16 Switching Element for ATM Exchanges · IEEE J. Sel. Areas Commun. 1991

Methods — techniques the papers use, named apart from their topics

queueing analysis · 0.0chip partitioning · 0.0
YearPublicationVenuePosition
1991 Implementation of a 16 to 16 Switching Element for ATM Exchanges
abstract
The authors describe the implementation of an asynchronous transfer mode (ATM) switching element with 16 inlets and 16 outlets at 600 Mb/s each. The single board switching element is used as a basic switching block in a connection-oriented ATM switching network. The design of the switching element was carried out by using advanced BiCMOS technologies. It is shown how the functional scheme is translated into a feasible chip partitioning and which design options were taken. In particular, the design of the cell switching facility and the queueing memory is treated in detail. A comparison between memory pooling or individual output queues is presented. By making the choice of the latter solution, the development schedule could be kept very tight. Second, the testability of the chips remains good despite the high gate complexity.>
P. Barri, J. A. O. Goubert
IEEE J. Sel. Areas Commun.1