Minimum mean square error estimators have been developed for non-uniform subband adaptive filters (SAF) in system modeling configurations. The next step towards practical implementation of non-uniform SAF involves developing an adaptive algorithm to control the non-uniform filterbank's bandwidths and decimation factors. This paper constructs such an algorithm using subband minimum mean square error (MMSE) bounds to suggest decimation factors. A numerical simulation shows that a non-uniform SAF can achieve lower MSE with lower complexity than an equivalent uniform SAF.

This paper describes the integrated teaching and learning laboratory (ITLL) of the College of Engineering and Applied Science of the University of Colorado (CU), Boulder. Not only does the building support and drive the curriculum but the design of the building was curriculum driven. In fact, the building itself serves as a laboratory instrument with more than 300 sensors embedded throughout the building and the opportunity to perform experiments on the building itself. All the sensor data are available on the Web. The ITLL is truly an example of Winston Churchill's quote-"first we shape our buildings and then our buildings shape us.".

The authors describe efficient polynomial algorithms for the extraction of topologically minimal multilevel Boolean equations and don't care conditions from the C-based hardware description language CHDL, which has control constructs switch, if-then-else, and go-to. They show that significant savings in CPU cost, area cost, and robustness may be obtained by applying these algorithms as a preprocessing step before using higher cost minimization tools such as BOLD or misII. The approach is based on a control-flow-graph construct with embedded set-use-graph information. The algorithms parse a CHDL description into a directed, nonseries parallel control flow graph. In cases where the graph is also acyclic, graph search and decomposition algorithms are used to derive a Boolean network representing the implied combinational logic. The derived equations are topologically irredundant in the sense that the topological identities are associated with the fork, and join nodes of the control flow graph are accounted for in the code generation. Without this feature, multilevel logic optimizers would have to flatten the control expressions down to primary inputs to discover these identities.>

A number of experiments have been conducted to answer several important questions about logic optimization and its application to high-level synthesis. The experiments are summarised and show that: logic optimization is competitive with manual design; stronger optimization methods give somewhat better average results (10%-30%) at much greater computational cost (8* and more); fast logic optimization methods can be used to estimate the average results of the more powerful, costly methods; and literal count is a good estimator of area before routing for standard cell designs.>

Discrete simulation of digital circuits is a vital tool in the design process. However, few people are aware of the modeling assumptions inherent in discrete simulation. Nor is there a widely accepted and consistent theory of modeling and simulation of discrete/digital systems. In this paper we concentrate on the basic ideas behind discrete modeling and present a discussion of the most popular algorithms used in writing simulators. In addition, we use the characteristics of discrete models to define the logic, functional, and behavioral levels of simulation. In closing, we discuss new issues in modeling and simulation.

This paper is concerned with the computational problem of maximizing the yield of circuits. A statistical Monte Carlo based approach is taken in order to compute yield estimates directly and to decrease dimensionality dependence. The main contribution of this paper is a yield extrapolation technique which is very effective in maximizing the yield along a search direction. This technique is based upon a quadratic model of the circuit. Statistical yield estimates are computed from the model and correlated sampling is used to extrapolate along the search direction. Two simple methods for determining search directions are discussed and these are used to demonstrate the overall method through several examples.

The efficiency of several variance reduction techniques (in particular, importance sampling, stratified sampling, and control variates) are studied with respect to their application in estimating circuit yields. This study suggests that one essentially has to have a good approximation of the region of acceptability in order to achieve significant variance reduction. Further, all the methods considered are based, either explicitly or implicity, on the use of a model. The control variate method appears to be more practical for implementation in a general purpose statistical circuit analysis program. Stratified sampling is the most simple to implement, but yields only very modest reductions in the variance of the yield estimator. Lastly, importance sampling is very useful when there are few parameters and the yield is very high or very low; however, a good practical technique for its implementation, in general, has not been found.

In this paper we introduce the concept of implication for MOS switch level circuits. The implication performed on these circuits is an extension of the classical implication now applied to Boolean logic networks. Given the ability to perform implication on MOS circuits we can then; generate functional macromodels of MOS circuits, use these macromodels to verify the Boolean function realized by the MOS circuit extracted from the mask set, generate, directly from the MOS circuit sets of tests for nodes stuck-at-1 and stuck-at-0 as well as transistors stuck open and stuck short. We present the conceptual frame work and algorithms for performing implication on MOS networks. We present examples of MOS implication and discuss extensions of the algorithm to test generation, and to a first order instead of zero order MOS network.

In this paper we investigate for the first time the applicability of the concepts and algorithms of Multiple Criterion Optimization to the problem of optimally trading-off magnitude and phase in IIR digital filters design. Particular attention is paid to the mathematical formulation of the simultaneous magnitude and phase design problem. Three different design criteria are introduced. The special modifications of a standard algorithm [9] necessary for filter design are discussed. Examples of what can be expected from magnitude-phase trade-offs are discussed. The results of this work is expected to be practical CAD tools for designing simultaneous magnitude and phase optimal filters and theoretical information about the optimal trade-offs between magnitude and phase.