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Zoran Jovanovic

dblp:63/3901 · DBLP profile ↗
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10ranked-venue papers
2as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 7 · 1 first-authorDatabases, data management, data science and information retrieval · 1 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1Human-computer interaction and ubiquitous computing · 1Theory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 91% Parallel and multicore computing · 9%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › interprocessor communication
communication algorithms
0.011994
Communication Aspects of the Star Graph Interconnection Network · IEEE Trans. Parallel Distributed Syst. 1994
Interconnection networks and networks-on-chip
routing and broadcasting
0.011994
Communication Aspects of the Star Graph Interconnection Network · IEEE Trans. Parallel Distributed Syst. 1994
Interconnection networks and networks-on-chip › network topology › cayley graph
star graph
0.011994
Communication Aspects of the Star Graph Interconnection Network · IEEE Trans. Parallel Distributed Syst. 1994
YearPublicationVenuePosition
2012 Formal specification of usability measures in model-driven development of context-sensitive user interfaces
abstract
Developing usability studies to evaluate user interfaces (UIs) is a task requiring a wide variety of skills. In this paper we propose conceptual architecture for design and integration of usability tests in model-driven development of context-sensitive user interfaces. Upon the extended model for development of context-sensitive user interfaces, we introduce a generic framework that developers can use to design usability tests. This is enabled by using common vocabulary for description of usability test models and human models. Basic principles of the proposed approach are given in brief. As an example, we give formal model of human working memory that can be used in design of various cognitive load metrics.
Mladjan Jovanovic, Dusan Starcevic, Zoran Jovanovic
AVI3
2012 An accurate performance model for network-on-chip and multicomputer interconnection networks
Slavko Gajin, Zoran Jovanovic
J. Parallel Distributed Comput.2
2006 Web-based grid-enabled interaction with 3D medical data
Branko Marovic, Zoran Jovanovic
Future Gener. Comput. Syst.2
2006 Explanation of Performance Degradation in Turn Model
Slavko Gajin, Zoran Jovanovic
J. Supercomput.2
2001 A heuristic algorithm for dynamic task scheduling in highly parallel computing systems
Zoran Jovanovic, Slavko Maric
Future Gener. Comput. Syst.1
1998 Visualization of 3D fields and medical data and using VRML
Branko Marovic, Zoran Jovanovic
Future Gener. Comput. Syst.2
1994 Fault Tolerance of the Star Graph Interconnection Network
Zoran Jovanovic, Jelena V. Misic
Inf. Process. Lett.1
1994 Routing Function and Deadlock Avoidance in a Star Graph Interconnection Network
Jelena V. Misic, Zoran Jovanovic
J. Parallel Distributed Comput.2
1994 Communication Aspects of the Star Graph Interconnection Network
abstract
Basic communication algorithms for star graph interconnection networks are developed by using the hierarchical properties of the star graph, with the assumption that one input channel can drive only one output communication channel at a time. With this constraint, communication algorithms for each node can be expressed only as sequences of generators corresponding to the communication channels. Sequences that are identical exploit the symmetry and hierarchical properties of the star graph and can be easily integrated in communication hardware. Their time complexities are evaluated and compared with the corresponding results for the hypercube.>
Jelena V. Misic, Zoran Jovanovic
IEEE Trans. Parallel Distributed Syst.2
1982 The architecture of a signal processor developed through simulation
abstract
Host machines of signal processors are closely related to algorithm characteristics, and therefore simultaneous development of architecture and micro-programs could be succesfully done through simulation. In the created simulator, the program modules correspond to hard-ware components, and they are activated only once during a microcycle by using an "Equivalent generalized pipeline stage" model. The architecture is briefly described, with more significance paid to the address generation.
Miodrag Carapic, Zoran Jovanovic, Zorica Mihajlovic
ICASSP2