The wavelength-routed optical network-on-chip (WRONoC) emerges as a promising solution for multi-core system communication, providing high-bandwidth, high-speed, and low-power transmission. As the number of cores in a WRONoC increases, however, some WRONoC topologies could be infeasible with bandwidth and crosstalk constraints if bit-level parallelism is not considered during topology generation. Previous work optimized the parallelism only for the radius selection of microring resonators but not for topology generation. To remedy this drawback, we present a parallelism-aware WRONoC topology generation flow. The proposed flow guarantees to generate a parallelism-optimal topology for full connectivity; and a parallelism-optimal topology for customized connectivity if the netlist meets certain conditions. Compared with the state-of-the-art methods, experimental results show a 67.5% improvement in parallelism.

The optical interconnection is a promising solution for on-chip signal communication in modern system-on-chip (SoC) and heterogeneous integration designs, providing large bandwidth and high-speed transmission with low power consumption. Previous works do not handle two main issues for on-chip optical-electrical (O-E) co-design: the thermal impact during O-E routing and the trade-offs among power consumption, wirelength, and congestion. As a result, the thermal-induced band shift might incur transmission malfunction; the power consumption estimation is inaccurate; thus, only suboptimal results are obtained. To remedy these disadvantages, we present a thermal-aware optical-electrical routing co-design flow to minimize power consumption, thermal impact, and wirelength. Experimental results based on the ISPD 2019 contest benchmarks show that our co-design flow significantly outperforms state-of-the-art works in power consumption, thermal impact, and wire-length.

The wavelength-routed optical network on chip (WRONoC) is a promising solution for signal transmission in modern System-on-Chip (SoC) designs. Previous works do not simultaneously handle all the following four main issues for WRONoCs: 1) correlations between the topological structure and physical layout; 2) tradeoffs between the maximum insertion loss and the number of wavelengths; 3) runtime scalability of wavelength assignment scheme; and 4) a fully automated flow to generate predictable designs. As a result, their insertion loss estimation is inaccurate, their wavelength assignment is inefficient, and thus, only suboptimal results are obtained. To remedy these disadvantages, we present a fully automated topological structure and a physical layout co-design flow with improved wavelength assignment schemes to minimize the maximum insertion loss and the laser power simultaneously with a significant speedup. The experimental results show that our co-design flow significantly outperforms state-of-the-art works in the maximum insertion loss, laser power, and runtimes.

As the VLSI technology continues to scale down, combined with increasing demands for large bandwidth and low-power consumption, the optical interconnections with wavelength-division multiplexing (WDM) become an attractive alternative for on-chip signal transmission. Previous WDM-aware optical routing works consist of three main drawbacks: they are based mainly on heuristics or restricted integer linear programming to handle optical routing, the addressed types of insertion loss, and WDM overheads are incomplete, and the crosstalk noise during concurrent signal transmission is neglected. As a result, no performance guarantees can be achieved on their WDM clustering results, the reliability of the optical network is impaired, and/or their computations are too time consuming. To remedy these disadvantages, we present a new WDM-aware optical routing flow to minimize the insertion loss, the WDM overheads, and the crosstalk noise with a significant speedup. In the proposed flow, the WDM-aware path clustering algorithm guarantees to find an optimal solution for 1-, 2-, and 3-path clustering and has the constant performance bound for most cases of 4-path clustering; the crosstalk-aware path assignment guarantees to minimize the number of crosstalk signal pairs within the given displacement bound. Experimental results based on the ISPD 2007 and 2019 contest benchmarks and a real optical design show that our optical router significantly outperforms published works in wirelength, insertion loss, wavelength power, crosstalk noise, and runtimes.

The wavelength-routed optical network-on-chip (WRONoC) is a promising solution for signal transmission in modern system-on-chip (SoC) designs. Previous works do not handle three main issues for WRONoCs: correlations between the topological structure and physical layout, trade-offs between the maximum insertion loss and wavelength power, and a fully automated flow to generate predictable designs. As a result, the insertion loss estimation is inaccurate, and thus only suboptimal results are obtained. To remedy these disadvantages, we present a fully automated topological structure and physical layout codesign flow to minimize the maximum insertion loss and the wavelength power simultaneously with a significant speedup. Experimental results show that our codesign flow significantly outperforms state-of-the-art works in the maximum insertion loss, wavelength power, and runtimes.

As the VLSI technology continues to scale down, combined with increasing demands for large bandwidth and low-power consumption, the optical interconnections with Wavelength Division Multiplexing (WDM) become an attractive alternative for on-chip signal transmission. Previous WDM-aware optical routing works consist of two main drawbacks: they are based mainly on heuristics or restricted integer linear programming to handle optical routing, and the addressed types of transmission loss and WDM overheads are incomplete. As a result, no performance guarantees can be achieved on their WDM clustering results, and/or their computations are too time-consuming. To remedy these disadvantages, we present a polynomial-time provably good WDM-aware clustering algorithm and a new WDM-aware optical routing flow to minimize the transmission loss and the WDM overheads with a significant speedup. The proposed WDM-aware clustering algorithm guarantees to find an optimal solution for 1-, 2-, and 3-path clustering, and has the constant performance bound 3 for most cases of 4-path clustering. Experimental results based on the ISPD 2007 and 2019 contest benchmarks and a real optical design show that our optical router significantly outperforms published works in wirelength, transmission loss, wavelength power, and runtimes.

The emerging design requirements with the FinFET technology, along with traditional geometrical constraints, make the FinFET-based analog placement even more challenging. Previous works can handle only partial FinFET-induced design constraints because some new constraints are intrinsically different from the traditional ones; as a result, directly extending previous methods to handle FinFET-induced constraints would incur solution quality degradation and runtime overhead. To remedy these disadvantages, we present a new hybrid graph (meshed tree) representation of a window mesh and CB-trees (namely, WB-trees) and a new placement flow with effective and efficient schemes to simultaneously handle FinFET-based design constraints and traditional ones. Experimental results based on industrial designs with various constraints show that our placer outperforms published works in both solution quality and runtime.

As interconnects dominate circuit performance in modern chip designs, placement becomes an essential stage in optimizing timing. Recent timing-driven placement (TDP) techniques focus mainly on optimizing late slack rather than early slack. This paper presents a TDP algorithm to improve the early slack while preserving an optimized late slack. The preservation is achieved by accurately predicting optimal Steiner tree topologies after each move in our TDP algorithm. An optimality-preserving pruning scheme for each move is proposed to speed up the optimization process, without sacrificing the solution quality. Experimental results show that our algorithm can substantially improve the early slacks and the overall quality scores of the top-2 winning placers of the 2015 ICCAD Incremental Timing-Driven Placement Contest, while preserving their late slacks.

In this paper, three disturbance estimation algorithms are experimentally evaluated by considering the control problem of a rodless pneumatic cylinder. Three disturbance estimation algorithms are then employed to compensate for this lumped disturbance: they are the traditional linear disturbance observer (TDOB), the integral sliding-mode disturbance observer (I-SDOB) and the IMP-based SDOB (IMP-SDOB). Experimental results are presented to compare these three algorithms in terms of positioning accuracy.

Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR gates, and buffer gates. If the logic gates at the same level are in different types, which have different timing behaviors, the control of clock skew becomes difficult. Based on that observation, in this paper, we present a novel clock tree design style, called type-matching clock tree, to ensure that the logic gates at the same level are in the same type. We prove that any clock control logic can always be transformed to our type-matching clock tree. Then, based on the idea of type-matching clock tree, we propose a zero skew gated clock tree synthesis algorithm. Compared with the industry-strength gated clock tree synthesis, experimental data show that our approach can significantly reduce the clock skew in every process corner with a small penalty on the clock tree area and the clock tree power consumption.