When a program's working set exceeds the size of its last-level cache, performance may suffer due to the resulting off-chip memory accesses. Cache compression can increase the effective cache size and therefore reduce misses, but compression also introduces access latency because cache lines need to be decompressed before using. Cache compression can help some applications but hurt others, depending on the working set of the currently running program and the potential compression ratio. Previous studies proposed techniques to dynamically enable compression to adapt to the program's behavior. In the context of shared caches in multi-cores, the compression decision becomes more interesting because the cache is shared by multiple applications that may benefit differently from a compressed cache. This paper proposes Thread-Aware Dynamic Cache Compression (TADCC) to make better compression decisions on a per-thread basis. Access Time Tracker (ATT) can estimate the access latencies of different compression decisions. The ATT is supported by a Decision Switching Filter (DSF) that provides stability and robustness. As a result, TADCC outperforms a previously proposed adaptive cache compression technique by 8% on average and as much as 17%.

Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (e.g., LRU) can lead to poor performance and fairness when the multiple cores compete for the limited LLC capacity. Different memory access patterns can cause cache contention in different ways, and various techniques have been proposed to target some of these behaviors. In this work, we propose a new cache management approach that combines dynamic insertion and promotion policies to provide the benefits of cache partitioning, adaptive insertion, and capacity stealing all with a single mechanism. By handling multiple types of memory behaviors, our proposed technique outperforms techniques that target only either capacity partitioning or adaptive insertion.

For academic computer architecture research, a large number of publicly available simulators make use of relatively simple abstractions for the microarchitecture of the processor pipeline. For some types of studies, such as those for multi-core cache coherence designs, a simple pipeline model may suffice. For detailed microarchitecture research, such as those that are sensitive to the exact behavior of out-of-order scheduling, ALU and bypass network contention, and resource management (e.g., RS and ROB entries), an over-simplified model is not representative of modern processor organizations. We present a new timing simulator that models a modern x86 microarchitecture at a very low level, including out-of-order scheduling and execution that much more closely mirrors current implementations, a detailed cache/memory hierarchy, as well as many x86-specific microarchitecture features (e.g., simple vs. complex decoders, micro-op decomposition and fusion, microcode lookup overhead for long/complex x86 instructions).