This paper presents a technique for representing multiple-output binary and word-level functions in GF(JV) (where N = pm, p is a prime number, and m is a nonzero positive integer) based on decision diagrams (DDs). The presented DD is canonical and can be made minimal with respect to a given variable order. The DD has been tested on benchmarks, including integer multiplier circuits, and the results show that it can produce better node compression (more than an order of magnitude in some cases) compared to shared binary DDs (BDDs). The benchmark results also reflect the effect of varying the input and output field sizes on the number of nodes. Methods of graph-based representation of characteristic and encoded characteristic functions in GF(iV) are also presented. Performance of the proposed representations has been studied in terms of average path lengths and the actual evaluation times with 50,000 randomly generated patterns on many benchmark circuits. All of these results reflect that the proposed technique can outperform existing techniques.

The focus of this paper is to present a bit transition count analysis for various error detection and correction (EDAC) schemes through a detailed simulation. The simulation also brings out the impact of various EDAC schemes - linear, BCH, m-out-of-n, Berger and SEC-MUED - on bit transition count with respect to number of FSM partitions under different partitioning objective functions for low power. A decrease up to 30 percent in bit transitions count under the three partitioning objectives has been observed.