A simulator named "TLSIM is described in this paper.TLSIM simulates GaAs circuits considering the interconnects as transmission lines.The simulator provides a simplistic way of updating signals at circuit nodes.The simulation method is applicable to general graph topologies for interconnects.The behavior of signal flow at transmission line junctions and at the active circuit interfaces is captured by the application of Kirchoff's current equations.Coupling among conductors and loss in transmission lines are discussed.Results on run time and accuracy are presented for GaAs direct coupled FET logic (DCFL) circuits.1

The authors deal with estimating currents in nMOS/CMOS IC logic circuits at three levels of hierarchies: gate level, macro level, and power/ground distribution level. Models are developed for estimating currents in a macro-cell (macro) in response to input excitations. Algorithms are developed to estimate the maximum current requirement for a macro and to identify the input excitation at which the maximum current occurs. The macro currents are used to estimate the maximum currents in the segments of power (ground) distribution systems. Some of the algorithms provide tradeoff between runtime and quality of solutions. Experimental results are included.>

Estimation of currents in NMOS/CMOS IC logic circuits at the gate and macro levels is considered. The estimates are to be used for reliable design of power and ground buses. An accurate and efficient model of a gate is used to develop algorithms to estimate the maximum currents. The algorithms provide a tradeoff between run time and the quality of solution. Experimental results are included.>