Battery management system (BMS) is a key component to keep battery packs operating in safe and enduring conditions. This paper presents a SystemC-AMS–based BMS simulation platform including both BMS control and cell modeling designed to support fault injection and modular protection analysis. Through single-bit fault injection experiments, only a small fraction (12.8%) of injected faults violate the safety conditions. And SOC estimation and ADC modules are identified as the most critical components with faults covering all severe conditions such as overcharge, overdischarge and overheating. After applying dual module redundancy (DMR), we can enhance the reliability and reduce safety violations from the original 92321 errors to 72020 and 7860 errors or 78.01% and 8.51%, respectively for ADC and SOC modules. With DMR protection for both the ADC and SOC modules, we can eliminate all safety violations.

In this paper, we proposed a novel probabilistic fault propagation method for circuit of the register transfer level (RTL), enabling early-stage fault injection analysis. For the proposed method, we formulate and compute the probability of fault propagating to the output of an RTL operator based on the input logic patterns. By computing the probability of operators level by level (keeping correct circuit evaluation order), we can estimate the propagation probability at destination registers for each injected fault. By the probabilistic propagation list, we can then construct a propagation graph for multi-cycle analysis to avoid lengthy fault simulations.In our experiments, the proposed method can have a speedup of 35X to 158X faster than a traditional fault injection method, while achieving an average of 94.94% accuracy in the prediction of propagation of an injected fault. Hence, the proposed method can be applied to select high-quality fault candidates and to quickly evaluate the reliability of different design choices.

We propose a complete flow of multi-core minimum operating voltage (Vmin) prediction method using a nondestructive stress test. We process stress-test fail-logs and generate features to predict Vmin. In addition, we select important features by Pearson correlation and F-regression. Then, select specified test patterns that correlate to each core’s Vminby genetic algorithms to reduce stress test time. Experimental results on advanced 4nm multi-core CPU designs show that the best average RMSE of our predicted Vmincan be as low as 8.30 mV. Also, we have achieved over 66% test pattern reduction rate.

Debugging is becoming increasingly important to identify functional errors of SoC caused by transient faults and to ensure system reliability. However, due to the complexity of a SoC, locating faulty signals and cycles can be challenging. Debugging flow and tool, e.g., EQED [1], applies signature blocks (MISR circuits) to capture errors and uses bounded model checking to identify transient fault candidates. In this paper, we proposed a reduction method to select essential signals for inserting and connecting signature blocks. The method identifies the propagation condition of faults and constructs a fault propagation graph (a tree of equivalent propagated faults) for the selection of essential transient faults. In our experiments of a RISC-V core, we can reduce the selected signals to about 2% on average, while maintaining more than 99% of debugging coverage.

There are several applications of functional simulation with transient faults including evaluation of the vulnerability and design error-tolerant measures, as well as debugging of electrical hardware issues. Yet, the simulation is extremely slow given the complexity of RTL circuits and a large number of transient faults proportional to the total execution cycles. Recently, fault reduction methods are developed with Architecturally Correct Execution (ACE) analysis. The method can identify only about 3 % of total faults deemed necessary for simulation. However, the analysis effort is still non-trivial and most of the time is consumed in the small single-cycle fault simulation. In this paper, we proposed to use FPGA emulation to speedup the above process. In the experiments, on a RISC- V core, for a set of 16K faults, the analysis time are reduced from 1 hours to 1min, On average, the fault emulation has a speed up factor of 60 compared with a software implementation.

To satisfy requirements of system reliability, the importance of debugging grows increasingly to identify functional errors of SoC caused by transient faults. Yet, due to the complexity of a SoC, efforts to locate faulty signals and cycles are also dominating the yield ramp up period. Debugging-assisted circuits and associated tools play an essential role to keep the costs down. Notably, QED [1] and EQED [2] methods can use observation points, hardware checkers, and MISR to limit the candidate faulty cycle range and to prove the faulty signal candidates through bounded model checking (BMC). In this paper, we proposed a transient fault list reduction method as a filter before we apply BMC to check the validity of faulty signals and cycles. The method identifies the propagation condition of faults and constructs a set of fault traces (a tree of equivalent propagated faults) to examine and classify the transient faults. The roots found in the fault traces can significantly reduce possible faulty candidates to check with BMC. In our experiments of a RISC-V core, we can reduce the time spent on BMC from 97 hours to 6 hours of simulation and graph analysis on average. Overall, we can reduce the initial faulty candidates to under 5% or less of original list.

It is essential to perform extensive RTL functional fault simulation for critical systems in order to analyze the vulnerability and design error-tolerant measures accordingly. Since the number of faults would be exceedingly large for a full simulation, fault sampling techniques are applied. However, little information are available for fault characteristics, so the sampling might not be effective: often producing no error output or similar output syndromes.In this paper, we utilized an advanced Architecturally Correct Execution (ACE) analysis to study the functional fault characteristics of registers on a RISC-V core. From the results for all registers, only less than 0.34% to 2.76% of total faults need to be simulated. We then further sample and simulate these remained faults at RTL to analyze the categories for failure output syndromes. We found that faults at non-architecture registers have much higher masked results (as high as 90%), as compared with architecture registers (16% – 40%). Therefore, it is suggested that fault sampling should consider register and fault characteristics for a more effective result.

Critical systems require extensive simulation effort with functional fault injection on RTL circuits during design stages in order to analyze vulnerability and engineer error-tolerant measures accordingly. Yet for a complex SoC, long simulation cycles are necessary for each injected fault. Therefore it is imperative to prune as many faults as possible to improve simulation efficiency and turn-around time for designers.In this paper, we propose a novel method (ACE-Pro) to reduce the functional fault list. The method extends architecturally correct execution (ACE) analysis by creating a propagation graph, where a node is a fault marked with an ACE bit at a cycle and a directed link between nodes represents the propagation condition to another register at the next cycle. By checking and propagating through the graph the properties of masking (a fault is masked by logic on its propagation path to next registers) and singly-equivalence (a fault is covered by another fault on the next register), we show fault reductions by 98.91% to 99.91% (49.2% to 88.4% from the reduced faults in Equivalent Regions) in our experiments on a RISC-V core.

Shrinking feature sizes and cell capacitances, lower operation voltages, and higher operation speeds intensify the influences of radiation-induced soft-errors. To guarantee the functional safety of electronic systems, designers need effective techniques to evaluate designs under errors. Fault injection is one of the standard assessment tools for system dependability. However, because traditional RTL fault simulation has become too slow for modern complex systems, we need abstraction models for early-stage system reliability analysis and design. In this paper, we present an accurate reliability assessment SystemC fault simulator. It features a dynamic mechanism for injecting faults and analyzing the produced errors to evaluate possible fault detection and tolerance designs. Our experimental results show that our simulator can achieve 470x speedup on accurate architecture register fault simulation, validated with the RTL model.

The IP session highlights three innovative test practices in Asia, which include a testing solution for the millimeterwave (76- to 81- GHz) without expensive instruments, an on-chip delay measurement method for in-field test and a power control method of at-speed scan test for IR violation reduction. These would be useful for automotive and IoT application device testing.

System-level verification of a modem product involves ensuring both the hardware and firmware work correctly and that the product meets signal performance requirements at low cost. In many ways, the firmware problem is harder - or at least more open-ended. We discuss a development methodology based on automatic generation and reusable components that has been used to implement several generations of software-defined radio (SDR) modem SOCs. Automation both ensures consistency between models and tools and enables fast turnaround when something changes.

With the advent of highly complex and dense modern CMOS circuits, defects caused by parametric and process variations, e.g., are more and more difficult to detect. Many hard-to-detect defects not sensitized through the critical paths can easily escape from the conventional testing methods. In order to reduce the product defect level, we introduce the notion of quorum sensing (QS) to circuit testing (sensing) for improving the quality and reliability. The proposed thermal quorum sensing (TQS) mechanism triggers a thermal chain reaction to expose the subtle variations in the circuit due to small defects, which can be observed by the common cell population behavior. A model is introduced to charactize the feature of TQS on circuit. The simualtion result verified by the ISCAS s9234 benchmark with 45nm CMOS standard cell library shows when the number of small defects injected is more than 489, the difference in total current will be higher than 2.08mA. It can discover the subtle faults compared with other state-of-the-art or traditional testing methods.

In this paper, we propose an efficient test flow for Cell-Aware Test (CAT) to drastically reduce the time for CAT-enhanced test generation at the cell level. In CAT, the detail transistor-level circuit simulation is used to find appropriate test patterns and it has been considered as very time consuming. To solve this problem, first, we exploit Switch-Level ATPG (SL-ATPG) and experimentally show that it can efficiently generate test patterns in the CAT flow. Second, based on layout-oriented defect generation method, we propose an algorithm to automatically inject those defects into the switching network used in SL-ATPG, for cells in the library. Third, note that the traditional ATPG is primarily based on the stuck-at-fault and transition-fault models, it is difficult to find small-delay faults. However, the same defects are likely to be detected by observing the short-circuit current, so we propose current-based checks for a pattern generation method which are able to detect the existence of a short-circuit path. Finally, we compare the simulation time of detailed circuit simulation and of SL-ATPG in CAT. The experiment is based on a commercial 180nm CMOS standard cell library. Moreover, it shows that SL-ATPG method can successfully reduce the simulation time by about 403X.

This paper proposes methods to drastically reduce the expensive analog fault simulation currently used to create cell-aware fault models. By exploiting low-power properties of common CMOS designs, most defects in the transistor-level netlist containing parasitics can be represented by just two canonical fault classes. Via simple circuit analysis, we show that faulty behaviors are completely predictable as the defect resistance parameter value varies from zero to infinity, thus eliminating the need for circuit simulation at multiple parameter values. The two canonical fault classes can be modeled by transistor switch stuck-open and stuck-closed faults. Rather than enumerating the full combination cell input patterns to search for defect detection conditions by analog fault simulation, switch-level test generation can obtain those input conditions directly, thereby reducing significantly the role of analog simulation to that of ranking conditions in terms of detection effectiveness.

System tests with boards are applied to capture defects in functional modes. Yet, these tests are usually costly with limitation on the production throughputs. Stressed structural tests (patterns produced by traditional ATPG) have been proposed to correlate with system tests and to replace them in production. However, due to low confidence level (small experimental samples and volatile chip variability conditions), we need a process to tune and apply stressed tests gradually. In this paper, we use SVM to classify stressed tests with the goal to select high-quality chips without the need of further system tests. The remaining (smaller batch of) chips will be processed by system tests for further defect screening. The proposed SVM method can be flexible in tuning the relative size of chip partitions.

In this paper we describe a novel scheme for collecting and analyzing a chip's failure signature. Incorrect outputs of digital chips are forced by applying scan patterns under non-destructive stress conditions. From binary mismatch responses collected in continue-on-fail mode, numeric data features are formed by grouping and counting mismatches in each group, thus defining a chip's “analog” failure signature. We use machine learning to explore prediction models of system-level test (SLT) failures by comparing signatures of chip samples from known SLT pass/fail bins. Important features that clearly separate the SLT pass/fail chips are identified. Experimental results are presented for a 28-nm 1.2-GHz quad-core low-power processor.

This paper offers some perspectives on the practice of data mining based on recent experimental research work to establish a link between system-level failures and structural scan test patterns. Beyond the obvious goal to obtain accurate results, knowledge discovery and data insights deserve equal if not higher emphasis. Domain knowledge plays a crucial role in guiding the use of multiple machine learning tools through the fog of data noise towards usable results. A description of data analysis performed on a 28-nm 1.2-GHz quad-core mobile processor serves to illustrate the perspectives.

In the hyper-competitive consumer mobile product space where aggressive schedules, mass volume, and short life-cycles are the norm, system-level testing (SLT) plays a key role in achieving time-to-market (TTM) goals. But SLT also impedes time-to-volume (TTV) and cuts into profit margins. This talk will describe our recent experimental research to establish links between post-silicon SLT failures and production structural patterns. Operating on-chip-clocked scan patterns under non-destructive stress conditions to force incorrect responses from all devices, we apply machine learning to discern SLT failure signatures in noisy scan output data. One goal of the work is to significantly reduce SLT effort and cost, thus achieving early TTV and increased profitability. Other possibilities include diagnosis to identify systematically vulnerable regions of the design for selective test targeting with more through patterns.

As technology further scales, inaccurate prediction of IR-drop effect during scan testing could cause significant under estimation of the critical path delay, and further leads to serious issues such as insufficient guard band application, test escape, chip mis-binning and more. In this paper, a novel layout-aware path delay test generation method is proposed to maximize the effect of power-supply noise on target paths during delay test. It is able to estimate supply noise fast by calculating transition propagation probability and running fault simulation. Based on such estimation, the correlation between path-delay fault (PDF) and transition-delay fault (TDF) patterns is calculated to find the best sequence to merge patterns. The final generated path-delay test is able to simultaneously increase the local and global power-supply noise, thus furthur capture the worst-case timing scenarios of the target path. Experimental results show that the final PDF pattern can increase the path delay significantly comparing with the nominal PDF pattern and the best randomly-filled PDF pattern.

This paper describes our deployment of data mining techniques during final test to predict system level test failures and customer returns for two recent mixed-signal system-on-chip products. Emphasis is put on practical considerations for simplifying test flow implementation while still meeting the twin goals of reduced test cost and improved product quality.