In this paper, we identify two main bottlenecks in the functional diagnosis flow and propose new ways to overcome these. Our approach completely eliminates the "primary input (PI) pattern generation and simulation" step and instead employs scan-dump values extracted from the tester. We utilize backward and forward logic implications of the scan-dump values to reconstruct more logic values for the circuit signals. Furthermore, we employ the reset state for the non-scan latches of the design to increase the number of specified signals in the overall circuit. Experimental results on stuck-at faults on industrial designs show that, in most cases, these reconstructed values are sufficient to correctly diagnose a fault, thereby avoiding hours of conventional functional diagnosis runtimes.

In this paper, we propose a novel framework to quickly extract illegal states of a sequential circuit and then use them as constraints during the SAT-based induction runs. First, we employ a low-cost combinational ATPG to identify unreachable partial-states among groups of related flip-flops. Second, we propose the concept of necessary-assignment looping to identify additional unachievable partial-states. Third, we extend the above unachievability theory to capture new non-trivial sequential logic dependencies among the circuit signals. Finally, we use a unified framework that utilizes all the above information and aims at maximizing the learning. All the learned illegal states are converted into constraint clauses and are replicated at all the unrolled transition relations to prune the searchspace. Experimental results show that, due to the added constraints, many safety properties can be proved at earlier depths and the induction run-times can be significantly reduced.

This paper presents a study of the implication based functional constraint extraction techniques to generate pseudo functional scan tests. Novel algorithms to extract pair-wise and multi-node constraints as Boolean expressions on arbitrary gates in the design are presented. Its impact on reducing the overkill in testing was analyzed, and report the trade-offs in coverage and scan-loads for a number of fault models. In the case of path-delay fault model, it was shown that the longest paths contribute most to the over-testing problem, raising the question about scan testing of the longest paths. Finally, the evaluation of the functional constraints on large industrial circuits show that the proposed constraint generation algorithm generate a powerful set of constraints most of which are not captured in the constraints extracted by designers for design-verification purposes

Fault collapsing of a fault-set helps in obtaining smaller test-sets as well as in reducing fault-simulation times. In this paper, we propose two new theorems by making use of the generalized dominance relations exhibited by a pair of faults. In order to learn several unique requirements for the faults in a low-cost manner, we employ a fault-independent analysis and propose heuristics to reduce the number of fault-pair comparisons required. Experimental results on ISCAS85, 89 & 93 benchmarks show that significantly more faults can be collapsed as compared to the existing methods, with smaller run-times in many cases. For most circuits, collapsing to less than 30% of the total number of faults is achieved

In this paper, we propose novel low-cost methods that combine static logic implications and binary resolution to significantly increase the number of non-trivial signal relations learned from the circuit. The proposed method first applies resolution techniques to learn new static single-node implications and then uses them to learn powerful multi-node implications. All the newly learned relations help in extracting more necessary assignments for a given fault, potentially increasing the chance for a conflict to occur among the necessary assignments. Experimental results on ISCAS89 and ITC99 benchmarks show that our method can identify significantly more untestable faults compared to existing non branch-and-bound based techniques.