Abstract This paper describes the basic design of Comp Consultants Standards Mumps system for Tano Corporation's Outpost 11 6800 based micro computer running under the Flex 2.0 floppy disk operating system with 64K bytes of random access memory. The Mumps system consists of an executive which includes I/O device handlers, and interpreter for Standard Mumps and a floppy disk storage system for global variables based on balanced trees with key compression by indexes and with 32 K of random access memory buffers to make up for the slow floppy disk access times. Comp Consultants Mumps involves some significant departures from previous Mumps implementations. In particular local variables and routine lines are stored in the same manner as global variables. For example the storage key for a routine consists of three parts: The routine name, a label, and a line offset number. Representing local variables and routines as global variables not only increases the available buffer space by eliminating special code to handle local variable storage, routine storage, and program editing; but also increases the utilization of the buffers by keeping in memory what is most often accessed regardless whether it is a local variable, a global variable, or program code. This unified representation of local variables and routines as global variables is described in detail in this paper.

Any switching function has weighted representations, i.e., symmetric representations for which some of the arguments are repeated. We call a logic network based on such a representation a weighted realization. It is shown that a weighted realization may be implemented using a full-adder network (called a moment generator) whose outputs are fed to a multiplexer. A procedure is given to synthesize the full-adder network using the fewest possible modules and with strong coalescing of modules into multibit adders.

Equational logic is an approach to combinational synthesis based on the equation f(x) = 1 rather than on the function f(x). The central problem of equational logic is to find a system of equations gi(x) = hi(x) (i = 1,2,...,k), of the simplest possible form, that has the same solutions as f(x) = 1. Given such a k-equation system, f(x) may be realized as the output of a k-wide digital comparator whose inputs are the 2k g's and h's constituting the system.

Given a combinational output function f and an input constraint φ = 0, there is a set G( f, φ) of output functions equivalent to f with respect to φ. A function belongs to G( f, φ), that is, provided its evaluations agree with those of f for all argument combinations satisfying the constraint φ = 0. We define the constrained-input problem as that of generating G( f, φ), given f and φ. A general solution for this problem is developed. Applications to the "don't-care" problem and to translator synthesis are discussed.

A combinational circuit realizing the switching function f(x) may be regarded as a solution verifier for the Boolean equation f(x) = 1. (*) The output of the circuit is 1, that is, if and only if the input-vector x is a solution for (*). We use the term "equational logic" to denote an approach to circuit synthesis based on (*) rather than on the function f(x). The central problem of equational logic is to find a system of equations gi(x) = hi(x) (i = 1,2,...,k), of the simplest possible form, that has the same solutions as (*). Given such a k-equation system, f(x) may be realized as the output of a k-wide digital comparator whose inputs are the 2k g's and h's constituting the system. The problem of finding a simple system of equations equivalent to a given equation was investigated more than a century ago by Willian Stanley Jevons, who called it "the inverse problem of logic." It was thought by Jevons and other 19th century logicians that the inverse problem is "always tentative," i.e., that it does not admit of algorithmic solution. It is shown in this paper, however, that the inverse problem may be solved as a covering problem by use of the "table of consequences" of Poretsky. As presently formulated, this approach is limited in practical utility by the large size of the tables involved. It appears that a practical solution technique requires a reformulation of the inverse problem.

General one-parameter solutions are exhibited for the RS, RST, and JK flip-flop input equations.

The family of solutions for a Boolean equation is commonly represented in a single formula involving arbitrary Boolean parameters. It is well known that n parameters suffice to construct a general solution for an equation in n unknowns. For some equations, however, a general solution may be constructed using fewer than n parameters. This paper describes a method for constructing reduced solutions, i.e., general solutions involving the fewest parameters possible.

A recent note by Soudack [1] discusses the application of Levine's method of canonical analog programming [2] to nonlinear and time-varying differential equations. Assuming that only the ai(t) are time-varying, Soudack states that canonical programming cannot be applied to the differential equation E ai(t) piy(t) = E bj(t) piu(t) (1) unless the condition m < n-q (2) is satisfied, where q is "the order of the highest derivative where a nonlinearity occurs, or is the highest derivative multiplied by a time-varying coefficient."

Quine shows [2], [3] that a logical formula expressed as a sum of products may be transformed into the sum of all its prime implicants by repeated application of the following two rules.

This paper describes an algebraic method for determining the effect produced on the logical structure of a synchronous, delay-memory sequential machine by a transformation of input, output, and state coding. The logical structure of a combinational transducer is specified by a 0, 1 ``pseudopermutation'' array called a logic matrix. Procedures are developed for computing the logic matrices for series, disjoint, and parallel combinations in terms of the logic matrices of the subunits. The logic matrix for a transducer exhibiting reduced dependence is characterized. Code transformation of the inputs, outputs, and states of a sequential machine is described in terms of permutation matrices. The logic matrix of the equivalent transformed machine is given as a function of the initial logic matrix and the matrices specifying the transformation.