EDBT 2026 Demo / reviewers in the wild / expert
Sharat Prasad
dblp:63/546
· DBLP profile ↗
5ranked-venue papers
2as first author
0since 2021 · last 1998
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-authorComputer networks · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Transport protocols and congestion control · 50% Internet architecture and protocols · 38% Network performance modeling · 12% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Transport protocols and congestion control › ATM congestion control
ABR flow control |
0.0 | 1 | 1998 | LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service · INFOCOM 1998 |
Internet architecture and protocols
ATM networks |
0.0 | 1 | 1998 | LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service · INFOCOM 1998 |
Transport protocols and congestion control
rate-based flow control |
0.0 | 1 | 1998 | LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service · INFOCOM 1998 |
Network performance modeling
stability analysis |
0.0 | 1 | 1998 | LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service · INFOCOM 1998 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0rate allocation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1998 | LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM ServiceabstractLAPLUS is a novel switch algorithm for flow control of the available bit rate (ABR) asynchronous transfer mode (ATM) service. It ensures a steady-state rate allocation satisfying the MCR-plus-equal-share criterion. It only requires constant-time processing and two tags to be stored per flow. It is naturally able to take peak cell rates of flows into account. LAPLUS solves in a novel way the problem of selecting a measurement interval. The solution allows it to contain queue growth and keep utilization high on one hand and control low speed flows and operate with stability on the other. We describe results of simulation study of LAPLUS. The results show it to be fair, responsive and stable. Sharat Prasad, Kamran Kiasaleh, Poras T. Balsara |
INFOCOM | 1 |
| 1994 | Estimation of circuit activity considering signal correlations and simultaneous switching
Tan-Li Chou, Kaushik Roy 0001, Sharat Prasad |
ICCAD | 3 |
| 1993 | Efficient Floorplan Enumeration Using Dynamic Programming
Sharat Prasad, Paul Kollaritsch, P. Anirudhan, D. K. Hwang, Steve Lusky, R. Farrow |
ISCAS | 1 |
| 1992 | SYCLOP: Synthesis of CMOS Logic for Low Power ApplicationsabstractA system called SYCLOP that synthesizes finite-state machines (FSMs) and combinational logic for low-power applications is presented. SYCLOP tries to minimize the area and the transition density at the internal nodes of a CMOS circuit. The minimization is based on the input signal probabilities and the transition densities. Using this system, a particular circuit can be optimally synthesized for different applications. Results have been obtained for a wide range of benchmark examples.> Kaushik Roy 0001, Sharat Prasad |
ICCD | 2 |
| 1988 | CLAY: a malleable-cell multi-cell transistor matrix approach for CMOS LAYout synthesisabstractCLAY takes a netlist partitioned down to the transistor level, a technology file with an arbitrary number of metal layers, and constraints on aspect and I/O signal positions to produce mask geometries. CLAY attempts to capture, in software, layout knowledge at the transistor level (allowing variable-shaped cells including heights) and at the floorplan level for VLSI sized examples. CLAY compares well with standard cell and manual approaches.> Paul Kollaritsch, Steve Lusky, Sharat Prasad, Neil Potter |
ICCAD | 3 |