In this paper we argue that a two-way second-level cache is a better design choice than a direct-mapped organization. We show two-way caches are as simple to implement as direct-mapped caches. If the cache controller contains tags, the data array can be organized as a single bank of standard SRAM. Otherwise, both tags and data can be organized as a single SRAM bank. Our simulation results show these novel two-way organizations outperform the direct-mapped approach.

We propose improvements to current trace-driven cache simulation methods to make them faster and more economicalWe attack the large time and space demands of cache simulation in two ways.First, we reduce the program traces to the extent that exact performance can still be obtained from the reduced traces.Second, we devise an algorithm that can produce performance results for a variety of metrics (hit ratio, write-back counts, bus traffic) for a large number of set-associative write-back caches in just a single simulation run, The trace reduction and the efficient simulation techniques are extended to parallel multiprocessor cache simulations, Our simulation results show that our approach substantially reduces the disk space needed to store the program traces and can dramatically speed up cache simulations and still produce the exact results.

We propose improvements to current trace-driven cache simulation methods to make them faster and more economical. We attack the large time and space demands of cache simulation in two ways. First, we reduce the program traces to the extent that exact performance can still be obtained from the reduced traces. Second, we devise an algorithm that can produce performance results for a variety of metrics (hit ratio, write-back counts, bus traffic) for a large number of set-associative write-back caches in just a single simulation run. The trace reduction and the efficient simulation techniques are extended to parallel multiprocessor cache simulations. Our simulation results show that our approach substantially reduces the disk space needed to store the program traces and can dramatically speedup cache simulations and still produce the exact results.

We propose and analyze a two-level cache organization that provides high memory bandwidth. The first-level cache is accessed directly by virtual addresses. It is small, fast, and, without the burden of address translation, can easily be optimized to match the processor speed. The virtually-addressed cache is backed up by a large physically-addressed cache; this second-level cache provides a high hit ratio and greatly reduces memory traffic. We show how the second-level cache can be easily extended to solve the synonym problem resulting from the use of a virtually-addressed cache at the first level. Moreover, the second-level cache can be used to shield the virtually-addressed first-level cache from irrelevant cache coherence interference. Finally, simulation results show that this organization has a performance advantage over a hierarchy of physically-addressed caches in a multiprocessor environment.

The inclusion property is essential in reducing the cache coherence complexity for multiprocessors with multilevel cache hierarchies. Some necessary and sufficient conditions for imposing the inclusion property for fully-associative and set-associative caches, which allow different block sizes at different levels of the hierarchy, are given. Three multiprocessor structures with a two-level cache hierarchy (single cache extension, multiport second-level cache, and bus-based) are examined. The feasibility of imposing the inclusion property in these structures is discussed. This leads to the presentation of an inclusion-coherence mechanism for two-level bus-based architectures.>