Demo Data from EDBT 2026 / reviewers in the wild / expert
John DeVale
dblp:63/5924
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 2006
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorSecurity and privacy · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 33% Memory systems · 33% Energy-efficient computing · 33% | |
| Software engineering, system software, and programming languages
1 paper |
Software testing · 100% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
3d-stacked memory |
0.1 | 1 | 2006 | Die Stacking (3D) Microarchitecture · MICRO 2006 |
Processor architecture and microarchitecture › multi-chip architecture
3d stacking |
0.1 | 1 | 2006 | Die Stacking (3D) Microarchitecture · MICRO 2006 |
Energy-efficient computing
thermal management |
0.1 | 1 | 2006 | Die Stacking (3D) Microarchitecture · MICRO 2006 |
Software testing › mutation testing › fault injection
fault injection testing |
0.0 | 1 | 2000 | The Exception Handling Effectiveness of POSIX Operating Systems · IEEE Trans. Software Eng. 2000 |
Software testing › non-functional testing
robustness testing |
0.0 | 1 | 2000 | The Exception Handling Effectiveness of POSIX Operating Systems · IEEE Trans. Software Eng. 2000 |
Methods — techniques the papers use, named apart from their topics
3d integration · 0.1ballista testing system · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | Die Stacking (3D) Microarchitectureabstract3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact. In this research, we study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional micro architecture between two die in a stack Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Gabriel H. Loh, Don McCaule, Patrick Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb |
MICRO | 4 |
| 2002 | Robust Software - No More ExcusesabstractSoftware developers identify two main reasons why software systems are not made robust: performance and practicality. We demonstrate the effectiveness of general techniques to improve robustness that are practical and yield high performance. We present data from treating three systems to improve robustness by a factor of 5 or more, with a measured performance penalty of under 5% in nearly every case, and usually under 2%. We identify a third possible reason why software systems are not made robust: developer awareness. A case study on three professional development groups evaluated their ability to estimate the robustness of their software. Two groups were able to estimate their software's robustness to some extent, while one group had more divergent results. Although we can overcome the technical challenges, it appears that even experienced developers can benefit from tools to locate robustness failures and training in robustness issues. John DeVale, Philip Koopman |
DSN | 1 |
| 2001 | Performance Evaluation of Exception Handling in I/O LibrariesabstractLack of data quantifying the performance cost of implementing good exception handling often causes developers to skimp on exception handling based on its overestimated perceived cost. In an effort to remedy this problem we provide performance data on the cost of building good exception handling into software. We use the Safe Fast IO library as a basis for this study. SFIO improves robustness by a factor of 3 to 10 over STDIO without sacrificing performance. We were able to improve the robustness of the critical SFIO functions by another factor of 5, thus quantifying and reducing robustness failure rates by a factor of up to 70 from standard I/O functions, with an average performance penalty of 1% as measured by the original SFIO benchmark scheme. Future processor architecture improvements will further improve checking speed, essentially eliminating performance as an obstacle to improving software robustness. John DeVale, Philip Koopman |
DSN | 1 |
| 2000 | The Exception Handling Effectiveness of POSIX Operating SystemsabstractOperating systems form a foundation for robust application software, making it important to understand how effective they are at handling exceptional conditions. The Ballista testing system was used to characterize the handling of exceptional input parameter values for up to 233 POSIX functions and system calls on each of 15 widely used operating system (OS) implementations. This identified ways to crash systems with a single call, ways to cause task hangs within OS code, ways to cause abnormal task termination within OS and library code, failures to implement defined POSIX functionality, and failures to report unsuccessful operations. Overall, only 55 percent to 76 percent of the exceptional tests performed generated error codes, depending on the operating system being tested. Approximately 6 percent to 19 percent of tests failed to generate any indication of error despite exceptional inputs. Approximately 1 percent to 3 percent of tests revealed failures to implement defined POSIX functionality for unusual, but specified, situations. Between 18 percent and 33 percent of exceptional tests caused the abnormal termination of an OS system call or library function, and five systems were completely crashed by individual system calls with exceptional parameter values. The most prevalent sources of these robustness failures were illegal pointer values, numeric overflows, and end-of-file overruns. Philip Koopman, John DeVale |
IEEE Trans. Software Eng. | 2 |