TurboBIST-Logic (TBL) is a software tool suite for incorporating logic built-in self-test (BIST) technology into digital Integrated Circuits and has been used by a variety of industrial designs globally since 2002. This abstract describes major features of TBL, and uses three industrial cases to show practical issues encountered and solved over the years. It also discusses an important new trend in going "hybrid," a flexible combination of capture-clocking schemes, with the goal to achieve an ever more optimal result over stand-alone schemes. Each of the three cases had its unique requirements for logic BIST, some needing to customize an existing solution, but all were set to achieve common BIST goals of at-speed testing, simple test interface to/from ATE, low test cost, high product reliability, and repeat testability investment reuse from IC, board, system, to in-field diagnosis.

This paper describes a timing analysis system (ACTAS: ACcurate Timing Analysis System). This system analyzes the logical behaviors of VLSI. It verifies timings at flip-flops and detects timing errors. Then, it calculates path delays of the partial combinational circuits generating the errors. If they do not satisfy timing constraints, the system detects error paths. In this system, the former method based on behavior analysis is called DYNAMIC TIMING ANALYSIS and the latter method based on path analysis is called STATIC TIMING ANALYSIS. By use of this system, it improves the timing analysis efficiency of the complicated timing of VLSI.