Accelerators for machine learning [artificial intelligence (AI)] inferencing applications are homogeneous designs composed of identical cores. Each core or processing element (PE) contains multiply-and-accumulate units, control logic, and registers for storing and forwarding weights and activations. Testing homogeneous array-based AI accelerator chips by running automatic test pattern generation (ATPG) at the array level results in a high CPU time and pattern count. We propose a constant-testable (C-testable) method for test generation at the PE level such that the ATPG effort does not increase with the number of PEs. Our results show that compared to the traditional array-level testing, the proposed method achieves up to$4.2\times $($3.5\times $),$1530\times $($2388\times $), and$170\times $($142\times $) reduction in the test pattern count, ATPG runtime, and test cycle count, respectively, for stuck-at (transition) faults in a$256\times 256$array, while preserving the test coverage. A reconfigurable scan architecture is introduced to enable the proposed C-testable solution for the entire accelerator array. The design-space exploration of a hierarchical test-compaction framework is presented. We also describe four debug solutions for fault localization and diagnosis.

Accelerators for machine learning (AI) inferencing applications are homogeneous designs composed of identical cores. Each core, or processing element (PE), contains multiply-and-accumulate units, control logic, and registers for storing and forwarding weights and activations. Testing homogeneous array-based AI accelerator chips by running automatic test pattern generation (ATPG) at the array level results in a high CPU time and pattern count. We propose a constant-testable (C-testable) method for test generation at the PE level such that the ATPG effort does not increase with the number of PEs. Our results show that, compared to the traditional array-level testing, the proposed method achieves up to 4.2× (3.5 ×), 1530 × (2388 ×), and 170× (142×) reduction in the test pattern count, ATPG runtime, and test cycle count, respectively, for stuck-at (transition) faults in a 256 × 256 array, while preserving the test coverage. A reconfigurable scan architecture is introduced to enable C-testing for the entire accelerator array.

In this paper, we propose a new method for test access and test scheduling in NoC-based system. It relies on a progressive reuse of the network resources for transporting test data to routers. We present possible solutions to the implementation of this scheme. We also show how the router testing can be scheduled concurrently with core testing to reduce test application time. Experimental results for the ITC'02 SoC benchmarks show that the proposed method can lead to substantial reduction on test application time compared to previous work based on the use of serial boundary scan. The method can also help to reduce hardware overhead.

Chip overheating due to excessive and unbalanced power dissipation has become a critical problem during test of complex core-based systems. In this paper, we address the overheating problem in network-on-chip systems by using on-chip multiple-frequency clocking. We control the core temperatures during test scheduling by varying the test clock frequency assigned to each core, so that the power dissipation of each core during test can be adjusted individually and thermal balance is achieved. We present a heuristic where the optimization process can be integrated with test scheduling. Experimental results for NoC benchmarks show that the proposed method can guarantee thermal safety and yield better thermal balance.

On-chip integrated network, the so-called network-on-chip (NoC), is becoming a promising communication paradigm for the next-generation embedded core-based system chips. The reuse of the on-chip network as test access mechanism has been recently proposed to handle the growing complexity of testing NoC-based systems. However, the NoC reuse is limited by the on-chip routing resources and various constraints. Therefore, efficient test-scheduling methods are required to deliver feasible test time while meeting all the constraints. In this paper, the authors propose a comprehensive approach to test scheduling in NoC-based systems. The proposed scheduling algorithm is based on the use of dedicated routing path that is suitable for nonpreemptive test. The algorithm is improved by incorporating both preemptive and nonpreemptive tests. In addition, BIST, precedence, and power constraints were taken into consideration. Experimental results for the ITC'02 system-on-chip benchmarks show that the nonpreemptive scheduling based on dedicated path can efficiently reduce test application time compared to previous work, and the improved method provides a practical solution to the real-world NoC-based-system testing with both preemptive and nonpreemptive cores. It is also shown that various constraints can be incorporated to deliver a comprehensive test solution

Network-on-chip is the new paradigm in core-based system design. Reuse of the on-chip communication network for NoC test is critical to reduce test cost. However, efficient reuse of the communication network for test of legacy cores is challenging. A mismatch between the NoC channel width and the core test wrapper width can adversely affect test efficiency. In addition, stringent power constraints on today's high-density systems exacerbate the test scheduling problem. In this paper, we propose a method for efficiently utilizing the on-chip network for power-aware test scheduling in NoCs. We make use of on-chip clocking to speed up test data transfer by selectively using faster clocks to test certain cores; other cores receive slower clocks to limit test power consumption. A method is presented to determine the clock rate distribution among cores. Experimental results for the ITC '02 benchmarks show that the new method leads to substantial reduction in overall test application time, while satisfying power constraints.

A novel design methodology for test pattern generation in built-in self-test (BIST) is proposed. Experimental results are presented to demonstrate how a fault in the test pattern generator (TPG) itself can have serious consequences, a problem that has not been investigated. A solution is presented here, where the faults and errors in the generator itself are detected during the test in the TPG itself. This provides several major advantages, including the ability to distinguish between TPG and circuit under test (CUT) faults. In addition, this will ensure that there is no loss of fault coverage for the CUT caused by a fault in the TPG. Two different design methodologies are presented: The first guarantees all single fault/error detection, the second capable of detecting multiple faults and errors. The proposed linear feedback shift registers (LFSRs) do not have additional hardware overhead. Importantly, the test patterns generated have the potential to achieve superior fault coverage for both stuck-at and transition faults.

We present a new technique for generating compact dictionaries for cause-effect diagnosis in scan-BIST. This approach relies on the use of three compact dictionaries and target both modeled and unmodeled faults. We present analytical results that provide useful guidelines for the design of these compact dictionaries. We also present experimental results for the larger ISCAS-89 benchmark circuits for the diagnosis of various types of unmodeled faults.

Network-on-a-chip (NoC) is becoming a promising paradigm of core-based system. We propose a new method for test scheduling in NoC. The method is based on the use of a dedicated routing path for the test of each core. We show that test scheduling under this approach is NP-complete and present an ILP model for solving small NoC instances. For NoCs with larger number of cores, we present an efficient heuristic. We then improve the heuristic by including BISTs and precedence constraints. Experimental results for the ITC'02 SoC benchmarks show that the new method leads to substantial reduction on test application time compared to previous work. The inclusion of BIST tests and precedence constraints provides a comprehensive solution for test scheduling in NoC.

We present a new technique for generating compact dictionaries for cause-effect fault diagnosis in scan-BIST. This approach relies on the use of three compact dictionaries: 1) D/sub 1/, containing compacted LFSR signatures for a small number of patterns and faults with high detection probability, 2) an interval-based pass/fail dictionary D/sub 2/ for the BIST patterns and for faults with relatively lower detection probability, and 3) D/sub 3/ containing compacted LFSR signatures for clean up ATPG vectors and random-resistant faults. We show that D/sub 2/, which is two orders of magnitude smaller than a maximal-resolution pass/fail dictionary, provides nearly the same diagnostic resolution as an uncompacted dictionary. We also show that, by using a 16-bit LFSR signature for D/sub 1/ and D/sub 3/, we obtain two to three orders of magnitude reduction in dictionary size, yet nearly no loss in diagnostic resolution. Together, these three compact dictionaries provide an. efficient solution to the problem of cause-effect diagnosis in scan-based BIST. These dictionaries can also be used to target unmodeled faults using scoring algorithms.

We present a new partition-based fault-diagnosis technique for identifying error-capturing scan cells in a scan-BIST environment. This approach relies on a two-step scan chain partitioning scheme. In the first step, an interval-based partitioning scheme is used to generate a small number of partitions, where each element of a partition consists of a set of consecutive scan cells. In the second step, additional partitions are created using a previously proposed random-selection partitioning method. Two-step partitioning provides higher diagnostic resolution than previous schemes that rely either on random-selection partitioning or deterministic partitioning. We show via experiments that the proposed method requires only a small amount of additional hardware. The proposed scheme is especially suitable for a system-on-chip (SOC) composed of multiple embedded cores, where test access is provided by means of a TestRail that is threaded through the internal scan chains of the embedded cores. We present analytical results to characterize two-step partitioning, and present experimental results for the six largest ISCAS'89 benchmark circuits and two SOCs crafted from some of the ISCAS'89 circuits.

A novel design methodology for test pattern generation in BIST is presented. Here, faults and errors in the generator itself are detected. Two different design methodologies are presented. The first one guarantees all single fault/error detection and the second methodology is capable of detecting multiple faults and errors. Furthermore the proposed LFSRs do not have additional hardware overhead. Also, importantly, the test patterns generated have the potential to achieve superior fault coverage.

We present a new scan built-in self-test (BIST) approach for determining failing vectors for fault diagnosis. This approach is based on the application of overlapping intervals of test vectors to the circuit under test, and it is especially suitable for faults that are detected by a relatively small number of pseudorandom test patterns. Two multiple-input signature registers are used in an interleaved fashion to generate intermediate signatures, thereby obviating the need for multiple test sessions. The knowledge of failing and fault-free intervals is used to obtain a set S of candidate failing vectors that includes all the actual (true) failing vectors. We propose a signature-analysis method based on overlapping sections and the principle of superposition to effectively prune the candidate set. We present analytical results to determine an appropriate interval length and the degree of overlap, as well as upper and lower bounds on the size of S. We also determine a lower bound on the number of true failing vectors through a simple graph model. Finally, we present experimental results for the ISCAS'89 benchmark circuits to demonstrate the effectiveness of the proposed scan-BIST diagnosis approach.

We present a new scan-BIST approach for determining failing vectors for fault diagnosis. This approach is based on the application of overlapping intervals of test vectors to the circuit under test. Two MISRs (multiple-input signature registers) are used in an interleaved fashion to generate intermediate signatures, thereby obviating the need for multiple test sessions. The knowledge of failing and non-failing intervals is used to obtain a set S of candidate failing vectors that includes all the actual (true) failing vectors. We present analytical results to determine an appropriate interval length and the degree of overlap, an upper bound on the size of S, and a lower bound on the number of true failing vectors; the latter depends only on the knowledge of failing and non-failing intervals. Finally, we describe two pruning procedures that allow us to reduce the size of S, while retaining most true failing vectors in S. We present experimental results for the ISCAS 89 benchmark circuits to demonstrate the effectiveness of the proposed scan-BIST diagnosis approach.