State-of-the-art cache compression methods compress multiple neighboring blocks often called as a sector into a single 64-byte block to effectively enlarge the cache capacity. A compressed block is created by storing 4-byte data patterns as dictionary entries and pointers to them for compressing multiple blocks. Furthermore, sector-based tag array maintains one-to-one mapping between tag and data arrays in order to preserve conventional cache access mechanism. We present a dual-block compression method which uses an entire uncompressed block as dictionary and compresses multiple neighboring blocks in a separate companion block to provide a larger dictionary for better compression ratios. Furthermore, we introduce the concept of buddy-set which expands the compressible candidate blocks across two adjacent cache sets to enlarge the scope of compression. Performance evaluations for the last-level cache show that the proposed dual-block compression with expansion of compressible candidates in the buddy-set can enlarge the cache by an average of 60% while current state-of-art compression proposal has only 29% improvement. The proposed scheme demonstrates 8.9% speedup over caches without compression.

Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is a promising memory technology, which has high density, low leakage power, fast read speed, and non-volatility, and is suitable for on-chip last-level caches with large capacity. Recently, Multi-Level Cell (MLC) STT-MRAM records two bits in a single cell to further improve the density for building even bigger on-chip caches. However, MLC worsens write energy consumption and endurance. The magnetization directions of its hard and soft domains cannot be flipped to two opposite directions simultaneously, which leads to the two-step transition problem for certain combinations of updating the 2-bit value. The two-step transition incurs extra flip in the soft domains, consume high energy, and negatively impact the life time of MLC STT-MRAM. In this paper, we present a new dimension to alleviate high write energy issue in MLC. During cache replacement, we select among a few candidates blocks close to the LRU position for replacement to lower the write energy with minimum impact on cache performance. We propose a novel block content encoding method to represent whole block with a few bits and use the encoding bits for better cache replacement. After picking the replacement block, we apply intelligent remap of each updated 2-bit values to further reduce the write energy. Performance evaluation results show this content-aware cache replacement can lower the write energy by 26.1% in comparison with MLC caches using regular Pseudo-LRU replacement policy.

The paper presents an innovative hierarchical feedback adaptation method that efficiently controls the dynamic QoS behavior of real time distributed data flow applications, such as sensor based data streams or mission-critical command and control applications. We applied this method in the context of the Real Time Adaptive Resource Management system, a middleware integrated services, developed at the Honeywell Technology Center. We present the analytical model for Automatic Target Recognition pipeline application and the impact of hierarchical feedback adaptation on the application behavior and its QoS parameters.

Resource allocation for high-performance real-time applications is challenging due to the applications' data-dependent nature, dynamic changes in their external environment, and limited resource availability in their target embedded system platforms. These challenges may be met by use of adaptive resource allocation (ARA) mechanisms that can promptly adjust resource allocation to changes in an application's resource needs, whenever there is a risk of failing to satisfy its timing constraints. By taking advantage of an application's adaptation capabilities, ARA eliminates the need for 'over-sizing' real-time systems to meet worst-case application needs. This paper proposes a model for describing an application's adaptation capabilities and the runtime variation of its resource needs. The paper also proposes a satisfiability-driven set of performance metrics for capturing the impact of ARA mechanisms on the performance of adaptable real-time applications. The relevance of the proposed set of metrics is demonstrated experimentally, using a synthetic application designed to represent time-critical applications in C31 systems.

Parallel and distributed computer architectures are increasingly being considered for application in a wide variety of computationally intensive embedded systems. Many such applications impose highly dynamic demands for resources (processors, memory, and communication network), because their computations are data-dependent, or because the applications must constantly interact with a rapidly changing physical environment, or because the applications themselves are adaptive. This paper presents a set of dynamic resource allocation techniques aimed at maintaining high levels of application performance in the presence of varying resource demands. It focuses on a class of applications structured as multiple pipelines of data-parallel stages, as this structure is common to many sensor-based applications. We discuss the issues involved in resource management for such applications, and present preliminary results from our implementations on Intel Paragon. Our approach uses feedback control-a real-time monitoring system is used to detect significant performance shortfalls, and resources are reallocated among the application components in an attempt to improve performance. The main contribution of this work is that it combines real-time monitoring of an application's performance with dynamic resource allocation, and focuses on practical implementations rather than simulation and analysis.

Ada Program Partitioning Language (APPL) has been designed as part of Honeywell's Distributed Ada project. The goal of the project is to develop an approach for reducing the complexity of building distributed applications in Ada. In the proposed approach, an application is written as a single Ada program using the full capabilities of the Ada language. It is not necessary to factor the underlying hardware configuration into the program design. Once the program has been completed and tested in the host development environment, it is partitioned into fragments and mapped onto the distributed hardware. The partitioning and mapping are expressed in APPL and do not require changes to the Ada source. The main thrusts of the project include the design of APPL and the development of language translation tools and the run-time system to support Ada and APPL for a distributed target. The authors present an overview of APPL, the goals considered in the design, and issues that impact its implementation.>