Externally asynchronous/internally clocked (EAIC) systems provide a means of reliable controller design and operation, and incorporate many advantages of both synchronous and fully asynchronous methodologies. The basic memory module of an internally-clocked system is the DFLOP the outputs of which are fully protected from metastability-generated anomalies. As a result, the only input constraint on an internally clocked system is a minimum pulse width corresponding to the frequency of the internal clock. In an internally clocked system, a clock event is not generated until all DFLOPs have resolved into alogically defined state. Because the period of the internal clock depends only on propagation delay through the components of the system, the clock always operates at a maximum possible frequency. Several internally clocked systems, involving both static and dynamic logic, are analyzed by using PSPICE simulations and the results of some real time tests are reported for comparison purposes. The operation characteristics of the DFLOP are analyzed at the component level, and system level comparisons are made with previous work. With submicron CMOS designs using dynamic logic, the internal frequencies of EAIC systems are predicted to exceed 300 MHz with throughputs of less than four ns.

A unique family of high-speed, microprogrammable asynchronous controller (MAC) modules is described in this correspondence. Each MAC module consists of two fundamental mode machines that communicate by means of a handshake interface that permits it to be driven by any programmable logic device including ROM's. Any state machine controller designed with a MAC module will operate free of critical races, essential hazards and output race glitches, and will have static hazard-free state variables. A multiplicity of programmable logic devices can be used to drive one or more MAC modules to achieve complex, but reliable, asynchronous, time-shared and/or parallel processing of data. Individual MAC modules having state variables numbering l,m,n,...can be cascaded to produce an available system state capacity of 2/sup lspl times/2/sup mspl times/2/sup nspl times/...states with up to (l+m+n+...)-way transition capability, all without compromising speed or reliability.>