This paper describes methods for reducing and measuring random jitter (RJ) of clock signals in multi-GHz test instruments. The methods are based on real-time averaging of parallel/synchronized signals with uncorrelated RJ. Prior work (up to 10 GHz) is extended by experimental demonstration up to 36 GHz with RJ below 200 femtoseconds (fs). The theory of operation is reviewed and experimental results are shown for 12 and 36 GHz. A de-embedding procedure is used to separate the jitter contribution of the test instruments (jitter "floor") from the measured values to obtain a better estimate of the actual ultra-low jitter values of the measured signals. The effects of amplitude imbalance, signal-skew, cycle-to-cycle jitter correlation, and component-added RJ are measured and analyzed.

This paper introduces a 4-stage jitter reduction circuit with 2 stages of frequency doubling to produce an ultra-low jitter, 54 GHz clock, synchronized to a 13.5 GHz ATE/BERT/FPGA reference signal. Jitter-reduction is achieved using 4 stages of real-time signal averaging, each with nominal reduction of 30%. The effects are cascaded to obtain ~3 times reduction in random jitter (RJ). The clock frequency is doubled twice to obtain a desired output frequency of 54 GHz, suitable for testing 54 Gigabaud and 108 Gigabaud devices (using double data rate, DDR clocking). Experimental results demonstrate reduction of random jitter below 200 femtoseconds.

This paper describes three methods for reducing random jitter (RJ) in Multi-GHz electronic test instruments. These are based on real-time averaging of periodic signals (clocks or reference signals). In each method, N multiple signals are phase-aligned and averaged to reduce jitter by (1/N)1/2. The first method uses multiple phase-locked sources and is evaluated at 1 GHz and 10 GHz. The second method uses integer-cycle delayed copies of a single source and has been shown effective at 4 GHz. A novel third method is introduced and characterized up to 10 GHz using multiple tuned delay line stubs. The three methods can be used individually or in various combinations as well as with traditional techniques (e.g., PLL-based methods). In one example, RJ~300 fs jitter is achieved using a single stage that combines two of the methods, starting with input RJSource~700 fs. Simulation of multiple-stage configurations suggest that “ultra-low” (100–200 fs) jitter may be feasible.

An adaptable platform for the development of customized ATE and test-support modules is described. The purpose of the platform is to provide a hardware framework for assembling combinations of specialized test modules for applications that are not well addressed by conventional general-purpose ATE alone. The platform can also be used to test, characterize, and calibrate individual modules prior to use within either a platform-based application or within a traditional ATE environment. The paper describes some of the salient features of the platform and one completed example for an all-optical packet-switching network called ¿Data Vortex¿ operating at 2.5 Gbps on each of 18 channels (>40 Gbps aggregate burst data rate). Two other example modules demonstrate even higher data rates. One is a dual-channel, bidirectional 5 Gbps FPGA-based module with loopback, jitter-injection, and 2:1 XOR multiplexing (up to 10 Gbps). This module exploits recent advances in FPGA technology that enable very high data rates at relatively low cost. Another example module synthesizes two 10 Gbps data streams using 16:1 SiGe serializers; and then combines these using an InP XOR gate to form a 20 Gbps test stimulus channel. While the platform and modules have interesting characteristics, individually they do not form a complete solution. However the various possible combinations, together with special-purpose modules, may help solve some of the most difficult test applications in the near future. Therefore, this paper tries to present the key features in a way that the reader may extrapolate to future test challenges.

The ability to precisely control the timing of digital signals is especially important for multi-GHz testing applications where errors are measured in picoseconds or even 100fs. While many solutions exist for continuous clock-type signals, delay of wide-bandwidth data signals is not so easy. In this paper we introduce a novel technique for adjusting the delay of ~7 Gbps data signals on a picosecond scale without significant distortion. The approach is based on a timing/amplitude dependency effect observed in a variable-gain SiGe buffer. A prototype is demonstrated with a variable delay range of about 50 ps. This circuit is enhanced by adding a "coarse" delay section, including four 33 ps steps, to provide the desired total range of ~140 ps. The end application requires several of these circuits for deskewing parallel buses of 6.4 Gbps ATE signals. The circuit is also useful for injecting a variable amount of jitter, limited by the fine-delay adjustment range.

A 2-channel module for testing serial and parallel signals up to 12.8 Gbps is described. It is intended to extend the capabilities of an existing 6.4 Gbps ATE, serving as a plug-in module in an active device interface board (DIB). This prototype circuit provides (1) direct connections to ATE channels for DC parametrics and low-speed functional testing, (2) 2:1 multiplexing of 6.4 Gbps to produce 12.8 Gbps stimuli with picosecond deskew, jitter-injection, and amplitude adjustment, (3) 1:2 fanout of 12.8 Gbps DUT response signals to allow testing by two 6.4 Gbps ATE channels, (4) full-rate low-jitter active loopback path with amplitude adjustment, and (5) auxiliary outputs for parallel monitoring of both transmitted and received signals. The basic logical structure is presented, and features of the module construction are described. A novel high-bandwidth adjustable delay circuit is described, that is used for deskew and XOR-based multiplexing. The performance of the module is demonstrated between 5.0 Gbps and 12.8 Gbps.

Controlling jitter on a picosecond (or smaller) time scale has become one of the most difficult challenges for testing multi-gigahertz systems. In this paper we present a novel method for reducing jitter in timing-critical ATE signals. This method uses a real-time averaging approach to combine multiple ATE signals and produces timing references with significantly lower random jitter. For example, we demonstrate a 3times reduction in jitter by combining eight ATE signals (each with sigma=4ps) to produce a low-jitter signal (sigma=1.3ps). The measured jitter reduction is shown to closely match that predicted by theory. This counter-intuitive (but welcome) result is of general interest for the design of any low-jitter system, and is particularly helpful for multi-GHz ATE where precise timing is so critical

This paper demonstrates the application of micro-electromechanical switches (MEMs) and SiGe logic devices for passive and active loopback testing of wide data buses at rates up to 6.4Gbps per signal. Target applications include HyperTransport, Fully-Buffered DIMM, and PCIexpress, among others. Recently-commercialized MEMs technology provides high bandwidth (>7GHz) in very small packages in order to support wide parallel buses. SiGe logic also supports >7 Gbps signals when active shaping of the waveform is required. Loopback modules are described with between 9 and 16 differential channels. Multiple cards handle very wide buses or multiple ports. Passive cards utilize MEMs for switching between the Loopback (self-test) mode and traditional ATE source/receiver channels (which are also used for DC parametric tests). It is this switching function that benefits from the MEMs increased density. Active loopback cards provide additional waveform-shaping functions, such as buffering, amplitude attenuation or modulation, deskew, delay adjustment, jitter injection, etc. The modular approach permits pre-calibration of the loopback electronics, and easy reconfiguration between design validation, characterization testing, and high-volume production testing.

Existing digital automated test equipment (ATE) can provide signals at about 1 Gbps or slightly higher. To accommodate multi-GHz test needs, some ATE provide options for a few faster channels (up to 3.6 Gbps). However, leading-edge parts may require 100s of these signals and in some cases at even higher speeds (5 and 10 Gbps). This work describes a modular approach that allows for as many as 144 multiplexing and/or sampling channels to be added to existing ATE. The modules developed, so far include multiplexers, demultiplexers, and high-speed samplers that each support multiple high-speed differential signals. Production units operating up to 2.5 Gbps were introduced. We provide more detailed characterization of these modules and describe new modules targeting 3.2 Gbps and 5.0 Gbps applications. Various re-clocking techniques and proprietary calibration methods are used in order to reduce timing errors (especially jitter) to the sub-50ps range. The general system configuration, and key features of the newly developed modules are presented.

A system for testing multi-gigahertz digital devices is described that uses conventional automated test equipment (ATE), supplemented with multiplexing and sampling logic. The approach is similar to earlier work [I] that demonstrated feasibility. However, this current paper solves many of the practical problems that limited application in production environments. Specifically, embedded logic is used for fastheliable auto-calibration of critical timing signals to achieve improved accuracy (typically 225~s). Variable output-level buffers are included in the multiplexing logic to provide a range of input levels to the device under test. Coaxial relays selectively switch between high-speed and DC modes of testing. Air- and liquid-cooling is used to maintain the electronics temperature, and thereby stabilize time delays. The production version of the system is scalable up to 144 high speed differential pairs, each operating at 2.5 Gbps. Overall timing accuracy (OTA) is about +loops, and is typically much better. Timing errors are found to be dominated by the ATE timing uncertainty, which is nevertheless improved through the use of the embedded calibration logic [patent pending]. The OTA includes peakto-peak jitter (at a bit error rate of 10'l2). The system is demonstrated by applying it to an AMCC 17x17 cross point switch that supports data rates as high as 3.2 Gbps. Additional electronic modules are under development that will further extend the maximum data rate (initially to 3.2 Gbps, then to 5 Gbps and above), while tightening the OTA.