This paper presents the design of a wideband pipelined multi-stage noise shaping (MASH) continuous time (CT) delta-sigma modulator (DSM). The quantization error of the overall$1^{\mathrm {st}}$-stage DSM is extracted as the input of the$2^{\mathrm {nd}}$stage, while the outputs of both stages are simply combined without using any digital filters. Overall, different shaping functions are generated for both QN without requiring any digital QN cancellation. Therefore, the pipelined MASH (PMASH) significantly mitigates QN leakage while retaining the decent loop stability of a traditional MASH. Additionally, several analyses have been made for the PMASH topology, e.g. the design guideline, the signal transfer function (STF), the robustness, etc. Clocked at 800MHz and enabling on-chip DAC calibration, the 65nm CMOS prototype with an exemplary 2-2 topology using multi-bit quantizers achieves 82.6 dB SNDR, 98.8 dB SFDR over 15.4 MHz BW at −0.5 dBFS 1.8 MHz input. The power consumption is 16.9 mW with 1.2V/1.5V supplies. It results in a competitive FoM${}_{\mathrm {S\vert SNDR}}$of 172.2 dB, while it avoids any off-chip calibrations.

This work presents a high energy-efficiency mixed-signal multiply-and-accumulate (MAC) macro in charge-domain for machine learning (ML) systems. It involves crucial features aimed at enhancing energy efficiency, throughput, and area efficiency, namely: 1) a parallel-serial (ParSer) scheme to augment the throughput by parallel input channels and reduce the power via serial analog accumulation rather than digital summation; 2) the weight-independent parallel digital-to-analog converter (DAC) sampling (WIPDS) to cancel weight nonlinearity during sampling and allow for resource-efficient DAC, significantly saving power and area; 3) a high energy-efficiency dynamic amplifier (DA) introduced to improve drivability and counteract attenuation of the serial accumulation, thereby attaining the desired accuracy with relaxed the afterward analog-to-digital converter (ADC) resolution and consequently reducing power consumption; 4) an optimized SAR ADC to reach higher energy efficiency. Fabricated in 28-nm CMOS technology, the prototype exhibits a peak energy and area efficiency of 362 TOPS/W and 3.23 TOPS/mm$^{2}$, respectively.

In this paper, we make a comparative study between existing architectures of two channel (2x) time-interleaved (TI) continuous-time (CT) delta-sigma modulator (DSM), namely, cascaded integrators feedforward (CIFF)-based architecture and cascaded integrators feedback (CIFB)-based architecture. The comparison is made in terms of the required DAC numbers, the input branches of the adders as well as the output swing of each integrator. Then, we propose a CIFF-FB-based 2x TI CT DSM through detailed derivations while the proportional integrator (PI) technique is used to simplify the overall architecture (e.g. the required DAC numbers). The proposed architecture has been simulated using behavioral models. It is shown that the CIFF-FB-based loop filter using the PI technique can be considered as a promising candidate implementing a 2x TI CT DSM, in terms of hardware consumptions and dynamic performance.

This paper presents a high-precision bandgap voltage reference (BGR) using a low-cost current trimming network. The high-order curvature compensation is implemented by injecting a current with concave temperature curve characteristics into the bandgap core circuit. Meanwhile, a current-based trimming circuit is proposed to obtain a precise reference voltage while reducing the circuitry complexity and area consumption. Compared with traditional resistor-based trimming networks, the proposed trimming scheme does not require large-area resistors and complex digital logic circuits. Compared with prior current-based trimming scheme, the proposed one does not require extra current mirrors. The proposed BGR was designed in a 180nm BCD process and post-layout simulation results show that the temperature coefficient (TC) is lower than 2.3 ppm/°C within a wide temperature range of -40℃ to 125℃. Additionally, the power supply rejection ratio (PSRR) of -69dB at 100Hz is achieved. The active area of the proposed BGR is 383 µm × 259 µm, where the area of the proposed trimming circuit only occupies 16%.

Many applications of machine learning (ML) have been integrated into edge devices with their low communication latency. In edge computation, the reprocessing of redundant data results in considerable energy waste. The prior research utilized a digital-delta-digital-sigma computing-in-memory (CIM) scheme to mitigate this redundancy. However, the 7-bit LSB-first ADC resulting from the near-zero-mean output distribution led to excessive area and latency overhead. The following digital adder further induced power consumption and latency. We propose a digital-delta-analog-sigma CIM macro incorporating an analog sigma converter (SC) for edge computation, involving a switch-capacitor integrator with a floating inverter amplifier (FIA) and a quantizer. The increased analog swing of the sigma integrator leads to the expanded output distribution, thereby maintaining comparable accuracy with a relaxed quantizer resolution. The simulation demonstrates that our strategy contributes to a 57.5% reduction in latency, a resolution decrease of 2 bits, and better energy efficiency. These improvements can potentially enhance energy efficiency and computational speed in edge computation devices.

Two-step linear-exponential architectures can be applied to incremental ADCs (IADC) to achieve high resolution. In the first step, the ADC works as a normal first-order IADC while, in the second step, the exponential integrator is used to implement extended counting. There exist two architectures for the implementation of the exponential step, where the only difference depends on whether the input signal is connected or disconnected. By conducting a comparative analysis on such two slightly different linear-exponential architectures, we propose to combine the exponential and slope techniques to further boost the resolution without degrading its original thermal-noise suppression ability and DWA effectiveness. Mathematical analysis and simulation results are presented to confirm the principle of the proposed IADC.

This paper presents a two-phase linear-exponential incremental analog-to-digital converter (IADC) with using second-order noise coupling (NC). In the first phase, it works as a first-order IADC. Then the second-order NC path is activated in the second phase to significantly expedite the accumulation speed. Moreover, during the second phase, the integrator is disabled to achieve a large maximum stable amplitude (MSA). Simulations demonstrated that the proposed architecture could achieve a higher signal-to-quantization-noise ratio (SQNR) while avoiding the noise penalty and keeping the high effectiveness of data weighting averaging (DWA) compared with the prior art with using first-order NC. Mathematical analysis and further simulation results are presented to confirm the theory of the proposed structure.

This article presents a power-delay-optimized monotonic-specific successive approximation register (SAR) ADC. The SAR feedback loop, comprising the proposed unbalanced N/P-MOS sizing technique, simultaneously reduces the SAR logic delay and the power to overcome the SAR ADC’s speed bottleneck. Benefiting from this technique, the sampling rate of the prototype 10b single channel 1b/cycle SAR ADC reaches 600 and 700 MS/s at 0.9 and 0.95 V supply voltage, while consuming 1.49 and 2.02 mW in 28 nm CMOS, respectively. Moreover, the 10b ADC achieves the SNDR of 56.39 and 56.42-dB at a Nyquist rate input frequency of 600 and 700 MS/s, leading to a Walden FoM of 4.6 and 5.3 fJ/conversion-step, respectively.

This work introduces a two-channel time-interleaved (TI) continuous-time (CT) 3rd-order delta-sigma modulator (DSM). It uses the information from one complete channel to predict the other channel based on the extrapolation principle. Note that, Cascaded Integrator of Distributed Feedforward (CIFF) topology is selected for the loop filter for the following reasons: 1) it could reduce the number of required feedback DACs as much as possible; 2) it allows to implement the zero optimization for the TI DSM such that the performance could be further improved. Furthermore, we employ the technique of error correction to address the issue regarding the delay-free feedback path, which originates from the extrapolating TI DSM. We present the derivations of the target TI CT DSM starting from a single-channel discrete-time (DT) DSM, while the compensation for excess loop delay (ELD) is considered. Fabricated in 65nm CMOS process, this modulator achieves an equivalent output sampling rate of 800MS/s, while the analog channel operates at 400MHz. It exhibits a signal-to-noise and distortion ratio (SNDR) /spurious-free dynamic range (SFDR)/dynamic range (DR) of 75.5dB/89.7dB/79dB over a 10MHz bandwidth. The total power consumption is 33.73mW from 1.2v/1.8v power supplies. It results in a Schreier Figure of Merit (FoM) of 163.7dB based on DR.

Concurrent neural signal instrumentation withstanding neural stimulation artifacts is essential for bi-directional neural interfaces to guarantee signal integrity. In this work, different front-end structures and stimulation artifact mitigation techniques are firstly reviewed to benchmark their step response speed. Then, a mixed domain level-crossing scheme is proposed to achieve fast dynamic response with minimized hardware overhead. The benefit of extending the phase detection range of the phase detectors in VCO-based continuous time$\rm \Delta \Sigma $modulators is investigated with stability and noise consideration. Then a shift-register-based phase counter is proposed to extend the phase detectors’s detection range, thereby increase quantization resolution and stability margin for in-band noise optimization. The proposed VCO-based neural front-end was fabricated in a 180 nm CMOS process. The prototype achieves$6.38~\mu $Vrms input-referred noise over 0.5 Hz-10 kHz bandwidth. With a linear input range of 120 mVpp, it exhibits a SNDR of 71.6 dB and a DR of 77.0 dB, which could be further extended up to 100 dB in the artifact adaption mode. Measurements verify that the proposed neural front-end can recover from rail-to-rail differential mode or common mode artifacts within 10$\mu \text{s}$(minimum$6.25~\mu \text{s}$) while the superposed small signal can be recorded uninterruptedly.

This paper presents a continuous-time (CT) 0–4 dual-stage Multi-stAge Noise-sHaping (MASH) Delta-Sigma Modulator (DSM), exhibiting +5dBFS maximum stable amplitude (MSA). In the context of 0–4 MASH topology, the 4-bit CT DSM employed as the second stage only processes 4-bit quantization noise (QN) of the front-end. Though the input signal exceeds the full scale (FS), the second stage still stays stable as long as the signal leakage does not overload it. Such feature guarantees the improved stability over a wider signal input range. In addition, to address the well-known QN leakage issue of MASH topology, we propose to combine the feedforward topology with proportional-integral-based excess loop delay compensation. It ensures high robustness of the proposed 0–4 MASH DSM without requiring any calibration. Additionally, we present an analysis of the anti-aliasing filtering (AAF) for the 0-X MASH DSM. It is found that the overall AAF of the 0-X MASH DSM is contributed from the second stage. Sampled at 400MHz, the 65nm CMOS experimental prototype measures signal-to-noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 76.7dB/87.3dB over a 10MHz bandwidth with 15.1mW power consumption. Moreover, with achieving +5dBFS MSA, the dynamic range (DR) is extended to be as high as 85dB, resulting in a state-of-the-art Scherier Figure of Merit (FoM) of 173.2dB based on DR.

This paper presents a hybrid CT/DT0-2 multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a passive noise-shaping successive approximation register (NSSAR) ADC as the $2^{\mathrm{n}\mathrm{d}}$ stage. The overall architecture is simple and robust. The front-end stage employs the continuous-time (CT) operation to perform coarse quantization and provide inherent anti-aliasing and easy driving. The back-end stage uses a second-order NS-SAR architecture, which excels at PVT robustness, power efficiency, and scaling friendliness. It also results in large relaxation of matching issues between the analog and the digital domains compared with conventional CT-MASH. Behavioral simulation results demonstrate the effectiveness and robustness of the proposed hybrid MASH architecture.

This paper presents a multi-rate hybrid multistage noise shaping (MASH) ΔΣ modulator (DSM) with high tolerance to noise leakage. The front-end discrete-time (DT) stage works in a low sampling frequency while the back-end continuous-time (CT) stage runs in a 4X higher clock frequency. Thereby, the quantization noise of the first stage could be easily extracted by using feedforward topology. Moreover, the required upsampling behavior between the two stages is intrinsically implemented in the CT second stage without requiring an additional 4X upsampler. This multi-rate hybrid DT/CT DSM combines the accurate feature of DT loop filter and the high-speed advantage of CT loop filter. Eventually, it results in a high-speed operation for wideband applications while exhibiting a much higher tolerance to noise leakage compared to a conventional CT MASH structure. Simulations results demonstrate the efficacy of the proposed architecture.

A low-power and fast-transient capacitor-less low dropout regulator (CL-LDO) has been proposed in this paper. A class-AB amplifier with adaptive embedded slew-rate enhancement (SRE) circuit is employed to improve both the transient response performance and load current range. The proposed CL- LDO has been implemented in a 55-nm standard CMOS process and occupies an active chip area of 0.012 mm2. It is capable of delivering 0-10 mA load current and recovering within 0.075 ps under maximum load current change with 1.3 V supply voltage and 0.1 V dropout, while consuming only 1-pA quiescent current, demonstrating its potential capability to be applied in low power duty-cycling wireless sensor applications.

Level converting is increasingly difficult in ultra-low voltage circuits with the aggressive scaling down of the input voltage. In this paper, we proposed a wide output range level shifter (LS) with the ultra-low input voltage. The proposed LS is integrated with a positive flip-flop function with a three-phase time borrowing scheme at the sampling edge. The working principle eliminates the current contention problem in the conventional cross-coupled level shifters, which allows a much higher output range at ultra-low input. The time borrowing technique also allows a relaxed timing constraint, which increases the timing margin and improves robustness against variation in ultra-low voltage circuits. The proposed LS is implemented with 45nm CMOS technology. Simulation results show that the proposed structure achieves a propagation delay of 10.01ns, power consumption of 11.23pW, and a power-delay-product (PDP) of 112,412ns-nW when converting an input signal of 200mV to an output level of 3 V.

This paper presents a discrete-time multi-stage noise shaping (MASH) delta-sigma modulator (DSM) with second-order digital noise coupling for wideband highresolution applications. By directly injecting the output of the second loop into the quantizer input of the first loop while choosing an appropriate signal transfer function of the second loop, a second-order digital noise coupling can be easily constructed without almost imposing any hardware complexity. With the help of the second-order digital noise coupling, the inherent quantization noise leakage in the MASH topology is significantly mitigated, thus resulting in less DC gain requirement for the integrators. Mathematical analysis and further simulation results are presented to demonstrate the effectiveness of the proposed MASH structure.

A delta-sigma modulator architecture reducing the impact of the digital-to-analog converter (DAC) non-linearity in a multi-bit delta-sigma DAC is presented. By cascading and deterministic dithering, only small signals are processed by the multi-bit DAC, thus a large dynamic range can be maintained; by suppressing the out-of-band noise before being processed by the multi-bit DAC, less shaped-noise gets inter-modulated by the non-linear DAC, thus the raise of noise floor is reduced. The proposed architecture provides a practical way to implement a high-resolution multi-bit delta-sigma DAC at low over-sampling rate (OSR). System level simulations in MATLAB show that an average ENOB=14.5-bits can be achieved with 0.2% (standard deviation) DAC element mismatch at OSR = 10.