This work in progress paper reports the preliminary steps towards the definition of a course that aims to empower systems thinking skills in engineering students and to stimulate interest and awareness in issues related to sustainability and ethics. A key aspect of Systems Thinking is to examine any problem to be solved from a wide perspective, considering all elements and conditions that can influence or that can be influenced by the possible solution, over time. In the case of engineering problems, this calls for the consideration of non-technical aspects, too. A Systems Thinking approach should therefore stimulate future engineers to take care of the potential environmental impact of the systems and devices they design. Similarly, they should make their design choices thinking about the wellness of people: not just the end-users of the products, but all the individuals implied in the whole supply and production chains. Furthermore, the general social impact of the developed technologies should be a point of attention as well. These considerations motivate the idea to propose a course that promotes, with a synergic approach, Systems Thinking, Sustainability and Ethics. This paper reports a preliminary step toward the whole course, i.e. a 6-hour teaching unit proposed in the context of guidance activities of the University of Padova. Although the limited duration did not allow to effectively develop any skill, it was a chance to introduce some students to the basic concepts and to share with them the possible connection between Systems Thinking and the sustainability and ethics issues. As discussed in the paper, the feedback from these students was really encouraging. The implementation of a whole course and the assessment of the achieved learning outcomes fall in the future developments of this work in progress contribution.

This paper proposes a step-up DC-DC converter that regulates the output voltage in order to supply a micro-power digital processor, starting from a low-voltage input source such as a harvester. The converter is based on a reconfigurable Fibonacci and binary switched-capacitor architecture and is fully integrated in a CMOS technology with the exception of three flying capacitors. The circuit includes all the auxiliary blocks needed in order to self-configure the conversion ratio and to power the system up. According to detailed simulation results, the proposed circuit regulates to 1.2V an input voltage from 0.3V up to 0.6V, with an average efficiency of 83%.

Data-weighted averaging is a widely used approach to cancel the non linearity arising from device mismatch in digital to analog converters (DAC), especially when the DAC is in the feedback path of Sigma-Delta modulators. However, when a low oversampling ratio is assumed in the modulator, spurious tone can arise due to algorithm ciclicity. The literature offers some solutions to such an issue, which however often become critical with respect to the corresponding hardware implementation. This paper proposes a modified bidirectional data-weighted averaging algorithm, whose circuit implementation preserves spurs immunity, while it equates the hardware complexity of the basic data-weighted algorithm. The paper reports the hardware implementation in a 65 nm CMOS technology. The algorithm performances are assessed by means of exhaustive simulations both at the transistor and at the system level.

This paper covers the design of dynamic element matching algorithms for the compensation of output level mismatch in the internal DAC of a ΣΔ modulator. This issue is considered from the definition of the algorithm itself, down to the design at the transistor level in a scaled CMOS technology. Indeed the main focus of the paper is to demonstrate that the hardware complexity is a major element to be considered when the most appropriate solution has to be singled out. All the statements in the paper are sustained by a design example of a second-order 4-bit ΣΔ ADC in a 65nm CMOS technology. Although this paper proposes no new DEM algorithms, it highlights some important issues in the practical design of ΣΔ multibit ADCs that are usually neglected in the literature, being many paper more focused on the algorithm theoretical performance.

We present a behavioral analysis of two different transceiver architectures for UWB breast cancer imaging employing a SFCW radar system. A mathematical model of the direct conversion and super heterodyne architectures together with a numerical breast phantom are developed. FDTD simulations data are used on the behavioral model to investigate the limits of both architectures from a circuit-level point of view. The result is that the simplicity of the direct conversion makes the receiver more robust toward the critical circuit impairments for this application, that is the random phase mismatches between the TX and RX local oscillators.

The increasing interest in impulse radio UWB communication links focuses the research interest on building blocks optimized for these specific systems. In this context, this paper proposes a ring oscillator for an impulse radio UWB transmitter. A multiloop ring oscillator is considered because it holds the potential of both high oscillation frequency and fast switch-on time. The novelty of the proposed inverter cell is found in the possibility to adjust the oscillation frequency digitally, rather than with an analog voltage. This leads to larger tuning range and less sensitivity to control noise. The digitally controlled oscillator is designed in 0.13μm CMOS technology and according to simulations the tuning range is from 4 GHz to 12.5 GHz. The power consumption is below 8 mW.

This paper presents an energy-efficient transmitter for UWB impulse-radio. The proposed circuit uses a novel combined mixer and power amplifier to generate a Gaussian pulse with 1.25GHz bandwidth and center frequency of 7.87GHz. The combined MXR-PA includes a monolithic transformer to reach a maximum output voltage swing of 3.2Vpp. The transformer has been designed so as to maximize the transmitter power efficiency and at the same time to realize a fourth-order ladder filter, in order to reduce out-of band emissions. The transmitter has been implemented in a 0.13μm CMOS technology, occupies an area of 0.14mm2and dissipates 1.92mW for a 10-pulse burst with 1.2V power supply.

A thorough analysis of the tank quality factor in LC oscillators using switched capacitor banks has been carry out taking into account the contribution of the switched capacitances in the off state. Analysis results, confirmed by circuit level simulations, clearly show that the contribution of the switched capacitances in off state strongly affects the quality factor of the capacitor bank, and thus of the tank, increasing it. General expressions of the quality factor of useful one-port reactive networks are also presented.

Shunt-shunt resistive feedback is used in this paper to design inductorless broadband LNAs in a digital 45 nm CMOS technology. Simulation results show 18 dB gain over a 10 GHz bandwidth, with NF-7 dBm in-band, while consuming 32 mW from a 1 V supply voltage.

An energy detector designed in a 0.18μm CMOS technology and intended for a non-coherent impulse-radio UWB receiver is presented in this paper. The proposed circuit exploits the quadratic current characteristic of saturated MOS transistors to square input pulses that cover the whole UWB bandwidth. The integral is computed with a Gm-C architecture connected to the squarer using a flipped voltage follower current sensor. A behavioural model of the receiver is developed in order to put the proposed circuit in the perspective of the complete system and to translate the transistor-level figures of merit in communication system parameters. The energy detector dissipates 5.4mW with a 1.8V power supply and a sensitivity of −88dBm is expected at the antenna

Trellis coded modulation (TCM) is a potential candidate for error correction in multilevel flash memories. TCM typically requires probabilistic decoding algorithms (e.g. BCJR), that can be conveniently implemented in the analog domain. In this work, we study the feasibility and complexity of the analog approach, proposing transistor-level solutions for the building blocks of the decoder. In the case of a TCM designed for an effective storage density of 3 information bits/cell, an analog decoder for a 196-bit field features an estimated current draw of2.

This work proposed to use a two-element array of coupled PLLs to generate quadrature signals. The main advantage of this technique is that phase noise performance and quadrature accuracy do not trade-off. A dual-mode quadrature VCO designed in a digital0.13μmCMOS technology is used as test vehicle to verify the viability of the proposed concept.

Squaring circuits are an important building block for impulse-radio UWB non-coherent receivers. This work proposes a squarer, based on the quadratic law of saturated transistors. Such a circuit has already been proposed for lower frequency applications, therefore this work focuses on the extension to ultra wide bandwidth, with particular care to the consequences related to the deviation from the ideal quadratic law of 0.18μm CMOS transistors. Simulation results prove that the proposed squarer can accommodate the whole UWB bandwidth, with a total power consumption of 1.7mW.

In this paper, the design of a fully analog iterative decoder for a serially concatenated convolutional code is presented. The decoder is reconfigurable in both block length and code rate. An interleaver size up to 2400 bit is considered. The decoder core implements a single SISO working on a window of the whole code trellis. It is then reused several times to decode the two constituent codes. The resulting decoder performs iterations, but it is fully analog. The extrinsic information exchanged in the decoding process is stored in an analog memory and permuted through a reconfigurable interleaver. Behavioral analysis of the decoder as well as precision and mismatch impact on performance are reported in the paper.

This work proposes an architecture for a multimode ADC. The architecture is based on the cascade of a single-bit 2-1 SigmaDelta modulator and a 4-bit flash converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence the proposed converter can fulfil the requirement of a wide range of standards: GSM, Bluetooth, UMTS and WLANa. The achieved dynamic range is 85dB, 72dB, 62dB and 59dB for GSM, Bluetooth, UMTS and WLANa, respectively. The corresponding power consumption is 4.6mW, 5.5mW, 7.4mW and 18.9mW

In this paper, we present an all-analog implementation of the rate-1/3, block length 40, UMTS turbo decoder. The prototype was designed and fabricated in a 0.35$mu$m CMOS technology and operates at 3.3 V. We also introduce a discrete-time first-order model for analog decoders which allows fast BER simulations, while taking into account circuit transient behavior and component mismatch. The model is applied to the rate-1/3 analog turbo decoder for UMTS defined in the 3GPP standard, and the discrete-time model predictions are compared with the decoder experimental performance and the transistor-level simulations. These results demonstrated that this model can be successfully used as a tool to both predict analog decoder performance and give design guidelines for complex decoders, for which circuit-level simulations are impractical.

In this paper, we present an all-analog implementation of the rate-1/3, block length 40, universal mobile telecommunications system (UMTS) turbo decoder. The prototype was designed and fabricated in 0.35$\mu$m complementary metal-oxide-semiconductor technology and operates at 3.3 V. We also introduce a discrete-time first-order model for analog decoders which allows fast bit-error rate simulations, while taking into account circuit transient behavior and component mismatch. The model is applied to the rate-1/3 analog turbo decoder for UMTS defined in the Third Generation Partnership Project standard, and the discrete-time model predictions are compared with the decoder experimental performance and the transistor-level simulations. These results demonstrated that this model can be successfully used as a tool to both predict analog decoder performance and give design guidelines for complex decoders, for which circuit-level simulations are impractical.

In this paper, we discuss the design and testing results of an analog 0.35 /spl mu/m CMOS turbo decoder for the rate-1/3, 40 bit UMTS turbo code. The prototype was successfully tested at nominal conditions (2 Mbit/s), with an overall power consumption of 10.3 mW at 3.3 V. The tested BER curve shows a limited performance loss (about 0.5 dB) with respect to that of the digital implementation. We also discuss a discrete-time model of the analog decoder which allows us to run BER simulations including circuit transient behavior and device mismatch in a very short time. Circuit-level simulations demonstrate the validity of our model. According to the discrete-time simulation, a significant contribution to the performance loss is due to device mismatch.

The design and test results of a three-metal, double-poly, 0.35 μm; CMOS analog turbo decoder for the rate-1/3, block length 40, UMTS turbo code, are presented. A discrete-time model of analog decoding networks is also presented. This model can be used as a tool to both predict chip performance in a short time and give design guidelines for complex decoders, for which circuit-level simulations are impractical.

In this work we propose an architecture for the acquisition and digitization of cardiac signals in a pace-maker, based on ΣΔ modulation. Due to the characteristics of such an application, the proposed system presents the typical design challenges of low-voltage, low-power circuits. The work demonstrates that, thanks to the narrow bandwidth typical of biological signals (50-150 Hz), oversampling conversion techniques can be advantageous in terms of power dissipation at a given dynamic range. The converter is designed in a 0.8 μm CMOS technology using the switched Op-Amp technique. The ΣΔ converter is a third order modulator with an oversampled frequency of about 8KHz and the circuitcan operate at a minimum supply voltage of 2 V, while dissipating 2 μW at most. According to simulation results the dynamic range is larger than 50 dB.