This paper presents a transistor-level verification flow to detect electrical overstress, static leakage and ESD-CDM issues in large low power SoC circuits. With innovative features like Spice patterns recognition and static voltage propagation by Calibre® PERC™, this approach brings significant added value to standard digital checkers that cannot capture some parts of the design in essence, such as analog IPs or third-party IPs designed outside power-intent driven flows. The results obtained on a 32nm CMOS circuit using multiple separate supplies with body biasing strategy, demonstrate the ability of this solution to cope with complex design architectures. As a matter of fact, some severe issues like hundreds of missing level shifters and weak input stages inside isolation cells were detected in few hours.

Several methods for increasing the speed of combinational static CMOS circuits, including techniques for partitioning gates on the basis of circuit complexity and input arrival time, are described. The target layout style is standard cell, rather than a PLA or gate matrix scheme. Use of a standard-cell-like image allows a two-level buffered hierarchy to be introduced which is beneficial to reducing circuit delays. Preliminary results from device sizing algorithms are also given. The device sizer employs a fast, accurate, waveform-simulation-based, table-driven delay calculator to determine gate delays. A summary of results shows that partitioning techniques yield delay reductions of 10 - 15% compared with another currently employed program. The sizing heuristics provide an additional 15 - 20% increase in circuit speed.