EDBT 2026 Demo / reviewers in the wild / expert
Yong B. Cho
dblp:64/114
· DBLP profile ↗
6ranked-venue papers
0as first author
0since 2021 · last 2005
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4Artificial intelligence and machine learning · 2Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
1 paper |
Graph algorithms and graph theory · 100% | |
| Artificial intelligence
1 paper |
Learning theory · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Parallel and multicore computing · 60% Integrated circuit design · 40% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Graph algorithms and graph theory › graph theory › graph transformation › graph modification
graph planarization |
0.0 | 1 | 1991 | Comments on 'O(n2) algorithms for graph planarization' · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 |
Graph algorithms and graph theory › planar graphs
planar graph algorithms |
0.0 | 1 | 1991 | Comments on 'O(n2) algorithms for graph planarization' · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 |
Machine learning › Learning theory
statistical learning theory |
0.0 | 1 | 1988 | Multinomial Conjunctoid Statistical Learning Machines · ISCA 1988 |
Parallel and multicore computing
parallel algorithms |
0.0 | 1 | 1991 | Comments on 'O(n2) algorithms for graph planarization' · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 |
Integrated circuit design › VLSI design
CMOS VLSI |
0.0 | 1 | 1988 | Multinomial Conjunctoid Statistical Learning Machines · ISCA 1988 |
Methods — techniques the papers use, named apart from their topics
parallel algorithm · 0.0statistical decision theory · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2005 | A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices
Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei |
J. Electron. Test. | 5 |
| 2003 | Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device TestingabstractThis paper extends the model in (Wajih Dalai et al, Proc. of Int. Test Conf., p.518-523, 1999) to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixture impact. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a defect level of 300 DPM (defects per million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Yong B. Cho, Sassan Tabatabaei, André Ivanov |
Asian Test Symposium | 2 |
| 2003 | Hardware design of CMAC neural network for control applicationsabstractCMAC neural network is one useful learning technique based on the cerebellum's motor behavior. CMAC uses a table look-up method to resolve the complex non-linear system instead of a numerical calculation method. The result is in better and faster controller for nonlinear dynamical system. In this paper, we propose a CMAC neural network for controlling a non-linear system. The simulation results show that the proposed CMAC controllers for a simple non-linear function and a DC motor speed control reduce tracking errors and improve the stability of its learning controllers. The validity of the proposed CMAC controller is also proved by the real-time tension control. Besides, hardware design of CMAC for control application has been implemented to confirm the proposed approach and architecture. Chan-Mo Kim, Kwang-Ho Choi, Yong B. Cho |
IJCNN | 3 |
| 1991 | Comments on 'O(n2) algorithms for graph planarization'abstractFor the original article see ibid., vol.8, no.3, p.257-67 (1989). The commenters point out that their parallel algorithm provides the maximum planar subgraph, and they compare it to the maximal planar subgraph provided by R. Jayakumar et al. in the above-mentioned paper. The space-time product complexity is also compared.> Yoshiyasu Takefuji, Kuo Chun Lee, Yong B. Cho |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 1988 | Multinomial Conjunctoid Statistical Learning MachinesabstractA statistical learning model called the multinomial conjunctoid is reviewed. Multinomial conjunctoids are based on a well-developed, statistical-decision-theory framework, which guarantees that conjunctoid learning will converge to optimal states over learning trials and the learning will be fast during these trials. In addition, a prototype multinomial conjunctoid module based on CMOS VLSI technology is introduced.> Yoshiyasu Takefuji, Robert J. Jannarone, Yong B. Cho, Tatung Chen |
ISCA | 3 |
| 1988 | Silicon Multinomial Conjunctoid Statistical Learning Modules
Yoshiyasu Takefuji, Robert J. Jannarone, Tatung Chen, Yong B. Cho |
Neural Networks | 4 |