Spurious tones arise in the output spectra of fractional-Nfrequency synthesizers due to nonlinear distortion of the accumulated quantization error introduced by the digital$\Delta \Sigma $modulator (DDSM). Both empirical results and rigorous mathematical foundations presented in previous works have demonstrated that such nonlinearity-induced spurs can be predicted by using the Periodic Nonlinearity Noise (PNN) concept. Using the continuous-time extension of the PNN, this paper establishes the distinguishing features of integer- and fractional-boundary spur families. Furthermore, it shows how to predict the locations and amplitudes of fractional boundary spurs in common multi-stage noise shaping (MASH) DDSMs.

To enable fractional-$N$frequency synthesis in a phase locked loop (PLL), the instantaneous division ratio of a multi-modulus divider is usually controlled by a digital$\Delta $-$\Sigma $modulator (DDSM). The accumulated quantization error (AQE) of the DDSM is injected into the loop. When distorted by inevitable nonlinearities within the loop, the distorted AQE gives rise to fractional spurs; these degrade the spectral purity and jitter of the synthesized signal. In this paper, we present a unified analysis of representative DDSMs in terms of their architectures and working principles. Their AQE’s variation range, variance (power), statistical distribution, spectral signature, and immunity to fractional spurs in the presence of nonlinear distortions are also characterized. In particular, we study and compare the classic family of Multi-stAge noise-SHaping (MASH) DDSMs and two state-of-the-art families: probability-density-shaping (PDS) and Enhanced Nonlinearity-induced nOise Performance (ENOP) DDSMs. Building on the prior art, we propose a novel family of Probability density And Spectral envelope Shaping (PASS) DDSMs which, while guaranteeing the maximum spur immunity for a given variation range of the AQE, also provide optimized shaping for fractional-$N$frequency synthesis in terms of both the probability distribution and spectral envelope of the AQE to avoid high frequency phase noise “bumps” and/or “plateaus”.

Fractional-N frequency synthesizers are notorious for producing spurious tones (spurs) whose frequencies depend explicitly on the fractional part of the frequency control word. This paper addresses spurs that appear in the spectrum when that fraction is zero. In principle, this setting should not produce any spurs other than the reference spur and its harmonics. In practice, if the divider controller is clocked, it introduces a set of spurs whose locations are determined explicitly by its initial state (usually called the "seed"). Experimental observations are consistent with theoretical analysis and simulations.

Interaction between the quantization error that the multi-stage noise shaping (MASH) digital ∆Σ modulator (DDSM) introduces into the system and nonlinear distortion in the loop generates fractional spurs. The Periodic Nonlinearity Noise (PNN) concept can be used to predict the locations and amplitudes of fractional spurs. This paper presents additional insight offered by PNN relating to the impact of the order of the MASH and the order of the polynomial distortion on the rolloff rate of the integer boundary spur (IBS) family.

A fractional-N frequency synthesizer inherently generates spurious tones because its output frequency is not an integer multiple of the reference frequency. Its spectral performance is degraded by these spurious tones that are caused by memoryless nonlinearities. This paper describes a CppSim-based behavioral model which can predict the effects of a user-defined arbitrary nonlinearity in terms of noise and spurs. The simulator is demonstrated for various divider controller architectures, such as multi-stage noise shaping (MASH), successive requantizer (SR), and enhanced nonlinearity-induced noise performance (ENOP). The enhancements successfully address the limitations of the basic CppSim model and provide various interfaces for accessing data related to VCO phase noise and spectrum analysis.

Fractional-N frequency synthesizers based on phase-locked loops exhibit spurious tones (spurs) that result from interactions between the accumulated output of the divider controller and nonlinearity in the loop. A number of methods have been proposed to modify the statistics of the divider controller signal so that interaction with a memoryless polynomial nonlinearity does not induce spurs. This tutorial paper reconciles two principal concepts in the literature: Familier and Galton’s mathematically rigorous fundamental limitation of DC-free quantization noise with respect to nonlinearity-induced spurious tones, and the heretofore empirical periodic nonlinearity noise function which has provided intuition and insight, as well as inspiring further innovation. It demonstrates the connection between the two concepts and highlights the strengths and limitations of the PNN as it relates to predicting the spur performance of fractional-N PLLs.

Digital ΔΣ modulators (DDSM) are used in applications that require a reduction of the wordlength of a digital signal. In the presence of non-idealities, the quantization error of the DDSM can interact with nonlinearities further along the signal chain and generate spurious tones in addition to excess noise. This paper introduces the INIS family of DDSMs that are inherently immune from nonlinearity-induced spurs. Some representative members of the family are analyzed through simulations; one is demonstrated with a hardware implementation. Their performances are compared with those of other well-known DDSM architectures.

Digital-to-time converters (DTC’s) used in fractional-N frequency synthesizers attempt to cancel the accumulated quantization error (QE) introduced by the divider controller with a view to recovering the integer-N phase noise (PN) performance. The resolution of the DTC needs to be sufficiently fine to suppress its own QE below the intrinsic integer-N jitter and, at the same time, sufficiently coarse to limit the DTC’s hardware needs. In this manuscript, we propose optimal strategies to determine the effective dynamic range, number of bits, quantization resolution, and unity delay of the DTC to achieve these goals; the additional jitter power introduced by input-dithered quantization methods to eliminate DTC-quantization-induced spurs is also considered. DTCs parameterized following these strategies can come close to realizing the spur-free integer-N PN with minimum hardware. Behavioral simulations confirm our analysis.

Digital-to-time converters (DTC’s) used in fractional-N phase locked loops (PLL’s) aim to zero the quantization error (QE) introduced by the divider controller in order to recover integer-N phase noise (PN) performance. Unfortunately, the inherent quantization behavior and integral nonlinearity associated with the DTC mean that the aforementioned QE cannot be canceled exactly; inevitably, the residual error gives rise to additional PN and spurious tonal phenomena. This tutorial paper uses DTC macromodels to analyze and distinguish the DTC’s sources of nonideality and the distinct adverse spectral responses induced by them. Different DTC enhancement techniques are shown to mitigate certain types of nonideality. A comprehensive design strategy incorporating these techniques is proposed, which mitigates the revealed excess PN and spurs introduced by the DTC’s nonidealities. The enhanced DTC enables the fractional-N DPLL to approach the fractional-spur-free integer-N PN performance limit. Behavioral simulations at both DTC-block and PLL-system levels confirm our analysis.

The mid-rise time-to-digital converter (TDC), e.g., a binary (bang-bang) phase detector and other few-bit TDCs, is commonly used as the phase detector (PD) in a digital phase locked loop (DPLL) because of the design simplicity and ultra-low consumption in terms of area and power. However, its hard quantization nonlinearity makes it nontrivial to estimate its linearized gain and the power of the quantization error (QE) that it introduces, and hence can make the linearized analysis at the DPLL-system level inaccurate. This tutorial paper formulates a minimum-mean-square-error estimator that is used to provide an accurate linearized analysis of the TDC; it takes into account the interaction between the quantization characteristic of the TDC and the statistical properties of the input jitter of a frequency synthesizer in both integer-$N$and fractional-$N$modes. A strategy for minimizing the TDC’s QE is provided; so-designed TDCs with equidistant quantization thresholds are able to achieve optimum jitter minimization at both the TDC and DPLL levels. Finally, the effective linear operating region of such TDCs is derived, which explains when the “hard quantizer” can be regarded as an almost linear PD and when not. Behavioral simulations at the TDC-block and DPLL-system levels underpin our analysis.

The digital-to-time converter (DTC) used in fractional-Nphase locked loops is designed to cancel the accumulated quantization error (QE) arising from the divider controller. In high-resolution synthesizers, the DTC performs an additional quantization when mapping the required high-resolution phase correction to its coarse-resolution output. This inherent hard quantization nonlinearity of the DTC, which is different from the DTC’s well-known soft integral nonlinearity, causes yet another kind of inexact cancellation of the QE and induces excess spurious tones that degrade the output phase noise and jitter. This paper reveals the root cause of the “DTC’s QE” and spectral manifestation of the DTC-quantization-induced (DQI) spurs. The waveform of the DTC’s QE is derived analytically; it shows that the DQI-spur pattern is (i) determined by the fractional frequency control word and the quantization resolution of the DTC, and (ii) is independent of the type, order, and modulus of the divider controller. In view of the fact that conventional DTC linearity enhancement techniques and stochastic divider controllers have no effect on DQI-spur mitigation, we propose a novel family of DTC-enhancement methods called input-dithered quantization (IDQ). When used in DTCs, the IDQ methods are effective in eliminating DQI spurs at source with negligible phase noise or jitter penalty.

Digital-to-time converters (DTC’s) that are based on a controllable delay line are used in fractional-N frequency synthesizers to cancel the quantization error (QE) introduced by the divider controller in order to recover the integer-N phase noise performance. To relax the control complexity and reduce the hardware demand, the DTC delay line can be segmented into a cascade of coarse and fine components. This paper compares two state-of-the-art DTC segmentation topologies and their control methods. We will show that the convergence of the least-mean-square algorithm auto-calibrating the DTC’s gain is an important issue that affects the success of the DTC-based QE cancellation when small fractional frequency control words are used. Behavioral simulations analyzed in the time and frequency domains underpin our study.

The Multi-stAge noiSe sHaping digital delta-sigma modulator (MASH DDSM) is the most used divider controller architecture for fractional-N frequency synthesis. It is well-known that a MASH DDSM divider controller can cause input-dependent spurious tones in the output spectrum of a synthesizer. This paper discusses MASH 1-1-1 DDSM-induced spurious tone patterns that are dependent on the initial conditions.

The divider controller in a conventional phase-locked loop fractional-$N$frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.

Bang-bang digital phase locked loops (BBDPLL’s) use a binary phase detector (BPD) to limit the complexity and consumption of area and power of the time-to-digital converter (TDC), which inevitably introduces more quantization errors (QE’s) than a conventional high-resolution TDC. Coarse-resolution TDCs with a few more bits than the BPD can help to mitigate the TDC-induced output jitter and phase noise (PN). This paper derives estimates of the RMS input and output jitters of such digital phase locked loops (DPLL’s) with mid-rise TDCs, including BBDPLLs, based on a multi-rate discrete-time model. A comprehensive jitter minimization strategy is provided. The impact of this type of jitter minimization on the enhancement of the output PN performance is studied for the first time. Behavioral simulations verify our analysis. Finally, we conclude with design rules of thumb and a design procedure that helps to mitigate the system jitter and to achieve an output PN spectrum that is dominated by the noises contributed by the reference and digitally controlled oscillator (DCO).

Phase locked loops for fractional frequency synthesis typically use Digital$\Delta \Sigma $Modulators (DDSMs) as their divider controllers. Different types and configurations of DDSMs have been presented in the past which have distinctive characteristics in terms of spectral shaping of their quantization errors, spur immunity and implementation costs. This paper presents a family of DDSMs that have provably high spur immunity and low folded noise when used in fractional-${N}$frequency synthesizers with polynomial nonlinearities.

This work introduces an accurate linearized model and phase noise spectral analysis of digital bang-bang PLLs, that includes both the reference and the digitally-controlled oscillator (DCO) noise contributions. A time-domain analysis of bang-bang PLLs is leveraged to derive closed-form expressions for the integrated jitter, leading to a precise estimation of the binary phase detector (BPD) equivalent gain. The theoretical predictions differ by less than 1% from the simulation results obtained using a behavioral model, in all typical cases: dominant reference noise, dominant DCO noise, and comparable contributions. An accurate discrete-time model that takes into account the time-variant effect arising from the multirate nature of a digital phase-locked loop (DPLL) is used, along with the provided estimation of the jitter, to predict the output and input-referred phase noise spectra. An excellent match with the simulated spectra is achieved for all the different operating conditions.

When the accumulated zero-mean output of a digital modulator encounters a nonlinear function, nonlinearity-induced spurs can arise in the spectrum of the resulting signal. These spurs occur with both periodic and aperiodic modulator outputs, and can appear in applications such as frequency synthesis at frequencies where filtering approaches are ineffective. The mechanism at the root of these spurs is the nonlinear transformation of the cyclostationary modulator-induced phase noise. An algorithm is presented which determines modulator parameters that guarantee a spur-free spectrum after the application of a memoryless nonlinearity to the accumulated modulator noise. The algorithm takes as its input a sampled representation of the in-loop nonlinearity function, and determines a matrix of probabilities to be applied by the modulator. The algorithm can handle arbitrary nonlinear functions and relies on straightforward, synthesizable operations. Simulations demonstrate the ability of the algorithm to program a modulator such that spur-free operation is obtained for an illustrative selection of nonlinearities.

The divider controller can contribute significantly to the phase noise and spur pattern in the output of a nonlinear fractional-N frequency synthesizer. A type of time-varying spurs caused by a MASH DDSM divider controller, termed wandering spurs, has been observed in simulations and measurements of real synthesizers. In this work, we propose and analyze several MASH-based divider controller architectures that mitigate wandering spurs in a fractional-N frequency synthesizer.

Spurious tones appear in the output phase noise spectrum of a fractional-N frequency synthesizer when nonlinearities are present in the loop. These spurs are generated by the interaction between the nonlinearity and the quantization error that the digital Σ modulator (DDSM) introduces into the system. This paper analyzes the spurious effect of polynomial nonlinearities on fractional-N CP-PLLs equipped with multi-stage noise shaping (MASH) DDSMs of different orders. This leads to a proof of immunity from spurs for PLLs based on higher order MASH modulators in the case of certain polynomial nonlinearities.

The presence of nonlinearities in a fractional-N frequency synthesizer leads to the generation of an additional component of noise that appears in the output phase noise spectrum. This nonlinearity-induced noise component manifests itself as spurious tones and an elevated noise floor, also known as folded noise. This paper presents a mathematical analysis of the folded noise generated in fractional-N phase locked loops (PLL) by the interaction between the quantization noise introduced by the divider controller and a nonlinearity. The analysis is performed for different digital$\Delta \Sigma $modulators (DDSM) and nonlinearities, providing expressions that allow one to predict the folded noise. These are compared with state-of-the-art predictions and simulation results.

Magnetic components are essential in many applications of electronics. Despite a very clear understanding of magnetic phenomena developed from first principles of Electromagnetics and Maxwell's equations, modelling of the magnetic field, flux and force in a particular system can be a very challenging problem. Often, direct calculations are avoided, and a phenomenological model describing magnetic interactions is used instead. There are a number of methods which can be used for the modelling of the magnetic field due to magnetic materials and inductors and which can provide detailed and predictive information on such systems. Multi-physics scientific packages utilising finite-element methods are among the most common tools as they can solve a wide range of different problems and employ universal numerical algorithms. As a trade-off, they are very resource-intensive and have a low speed of execution. As an alternative, one can develop simulation techniques utilising magnetic dipoles or equivalent currents. These methods are less resource-intensive and very fast; however, they also have their limitations. This paper presents a method of equivalent currents developed for the fast calculation of the magnetic field and flux. We show the application of the method to inductors and permanent magnets that have a particular importance in power electronics and electromagnetic kinetic energy harvesting.

The MASH Digital Delta-Sigma Modulator (DDSM) based divider controller represents a speed bottleneck in state of the art commercial PLL-based fractional-N frequency synthesizers. As next generation systems require higher phase detector frequencies, there is a need to make ever faster divider controllers. This paper describes a fine-grained nested cascaded MASH DDSM which is significantly faster than state of the art divider controllers, thereby eliminating the current speed bottleneck.

Frequency synthesizers based on finite state machines are notorious for producing spurious tones (spurs). These spurs can be inherent in the architecture or may result from interactions between quantization noise and nonlinearities. This paper presents recent results, including descriptions of the problems and emerging solutions thereto.

This paper presents a computationally efficient method to determine how the pattern of spurs in a fractional-N frequency synthesizer depends on the local nonlinearity of the phase-frequency detector and charge pump (PFD-CP). It also presents a case study using a transistor-level model of a common PFD-CP architecture.

It has been shown in the literature that a cross-coupled CMOS LC VCO will outperform an equivalent Colpitts VCO. In the case of bipolar devices, the jury is still out. This paper reports a comparative analysis of phase noise (PN), tuning range (TR), dissipated DC power and Figure of Merit (FoM) in cross-coupled and differential Colpitts LC VCOs topologies designed in 180 nm Si-Ge HBT technology for operation around 5 GHz. SpectreRF simulations show that the cross-coupled topology exhibits a minimum PN equal to -108 dBc/Hz, a tuning range of 17.5% and a dissipated DC power of 12.6 mW, with a FoM equal to 204 dB, while the Colpitts topology exhibits a minimum PN over the tuning range equal to -113 dBc/Hz, a tuning range of 21.6% and a dissipated DC power of 14.1 mW, with a FoM equal to 212 dB. This suggests that, for the considered technology, the differential Colpitts can exhibit better overall performance than the cross-coupled VCO.

Interaction between the requantizer's periodic output and charge pump mismatch nonlinearity in a fractional-N frequency synthesizer causes it to exhibit an elevated inband noise floor and spurs. In this paper, we consider three leading analytical predictions from the literature. By comparing simulation results with analytical predictions, we show that the two most common approaches fail to deal correctly with offsets, while the method based on Price's theorem works well.

The standard design methodology for fractional-N frequency synthesizers assumes that the filtered shaped quantization noise from the requantizer is masked below the spectral envelope of the underlying integer-N synthesizer. Fractional-N frequency synthesizers are notorious for exhibiting an elevated noise floor and an unpredictable pattern of spurs. In this paper, we argue that designers should not be deluded by the overly conservative predictions of the simplified linear model but should instead consider nonlinearities as early as possible in the design process.

Pseudorandom dither generators are widely used to break up periodic cycles in digital delta sigma modulators in order to minimize spurious tones produced by underlying periodic behavior. Unfortunately, pseudorandom dither signals are themselves periodic and therefore can have limited effectiveness. This paper identifies some limitations of using pseudorandom dither signals that are inherently periodic.

The frequency synthesizer is one of the most challenging blocks in wireless transceivers; it works as a local oscillator in both the receiver and transmitter. It is generally based on a charge pump phase-locked loop (CPPLL) structure. If we can change the structure of the CPPLL or synthesizer to achieve fast locking, it can be used in applications to improve the locking time. Several methods have been introduced to increase the speed of the locking process. One way to achieve fast locking is to use a bang-bang frequency comparator (BBFC) in the feedthrough path to increase the locking speed. However, using the BBFC leads to unwanted ripple in the control voltage applied to the VCO; this ripple, in turn, leads to worse phase noise. In addition, an offset in the BBFC can produce cycle slipping. Applying a proper deadzone in the BBFC can help the system to overcome the unwanted ripple and cycle slipping. Simulations in MATLAB confirm that applying a deadzone equal to or larger than the frequency offset can suppress the unwanted ripple.

In this paper we introduce the architectures of TDC and accumulator-based ADPLLs. Then, we briefly describe the block and timing diagrams of Gated-Ring-Oscillator-based and Local Oscillator-based TDCs. We present the governing equations of both TDCs and we calculate the resolution of the "first order noise shaping TDC plus moving average filter" system. We show briefly the effect of the phase error on the output of the "LO TDC plus moving average filter" system and we propose an extended LO TDC that can measure the phase error. We derive equations to predict the resolution of the extended LO TDC and we confirm the predictions with Matlab simulations. Finally, we compare in simulation the power spectral densities of the phase errors of a Gated-Ring-Oscillator-based ADPLL and of an accumulator based ADPLL with the extended LO TDC.

This paper presents a design methodology for dithered bus-splitting Multi stAge noise SHaping (MASH) digital delta-sigma modulators (DDSMs). Rules for selecting the appropriate wordlengths of the constituent DDSMs are derived which ensure that the spectral performance of the bus-splitting architecture is comparable to that of the conventional design but with less hardware. Behavioral simulations are presented which confirm the theoretical predictions.

We present a nonlinear analysis of quadrature Voltage-Controlled Oscillators (QVCOs) made up of two VCOs mutually coupled at their second-harmonic frequency through a direct coupling circuit. The analysis of the two VCOs, each of which is considered separately, as an injection locked oscillator, reveals some relevant aspects of their behavior related to the steep nonlinearity of the cross-coupled devices, as well as to common-mode voltage at the drain terminals. These aspects influence the synchronization condition of the overall system of the two VCOs, whose oscillation frequency significantly differs from the resonant frequencies of the individual tanks.

LC injection-locked frequency dividers (ILFDs) are attractive in frequency synthesizers because of their low power consumption compared to conventional digital dividers. The drawback of LC ILFDs is the narrow widths of their locked regions. One of the techniques to increase the locking range in these dividers is to use direct injection. In this paper, we present a simplified model of direct injection in an LC ILFD. Simulation results obtained from canonical ordinary differential equations match SPICE simulations qualitatively.

The HK-Multi stAge noise SHaping (MASH) Digital Delta-Sigma Modulator (DDSM) uses output feedback to make the quantization step appear prime, thereby maximising the cycle lengths for constant inputs. This structure uses a cascade of modified first-order error feedback modulator (EFM1) blocks with one-bit quantizers. Multibit quantizers are often used in DDSMs as the increased number of levels allows the quantizer to behave more linearly, thereby improving the stability of the modulator. In this paper, we analyse a HK-MASH DDSM with multi-level quantizers and show that the cycle length is always NL, regardless of initial conditions and the input value, where N is the cycle length of each stage and L is the number of stages in the DDSM.

This work describes an efficient method to estimate and compare the locking range of Injection-Locked-Frequency-Dividers. The method can be exploited during the design phase to explore rapidly how the locking range varies for many possible parameter settings and injection strategies.

According to the well known Barkhausen criteria, an oscillator requires a loop gain of greater than 1 to start up. In order to ensure start-up, the literature invariably advises a gain value of around 3. However, no valid argument exists to support this figure. This work demonstrates that this figure, in the case of the voltage-biased differential LC CMOS oscillator, may have some physical significance. Using a simplified model of the oscillator, a direct relationship between gain and power conversion efficiency is established. It is shown that the oscillator has a unique power conversion efficiency maximum and that this maximum corresponds to a gain of approximately 2.75. Extensive SpectreRF simulations support the claims.

There has been much interest recently in developing injection locking frequency dividers (ILFDs) since they can consume less power than digital dividers. However, the limited locking range is the main drawback for ILFDs. In this paper, the locking range for an LC oscillator based ILFD is calculated for different divide ratios. The reason that the locking range for dividing by two is much larger than the fundamental and divide by three locking range is explained for the first time. We also provide design rules for ILFDs. Measured results show close correspondence between experiment and our theoretical analysis

Abstract — Being able to test the intrinsic performance of a device under test (DUT) has always been the main goal of a test engineer. Achieving this goal is becoming increasingly difficult due to tester and test setup limitations. In particular, with the wide spread availability of high-precision, medium-speed ADCs in tiny packages, the properties of the contactor between the DUT and the device interface board (DIB) is becoming an increasing concern as it introduces significant discrepancies between intrinsic device performance and the performance measured in production test. This paper presents results of a 12-bit ADC case study carried out at Analog Devices. For a representative sample set of devices, the linearity is characterized using a customer-like setup and a production test setup, successively. The discrepancy between device measurements using the two setups is first determined. Using a model-based testing approach, the noise-induced test uncertainty can be reduced [1]. We present a modification of this modelbased technique that predicts the performance of a device measurable using the customer-like setup from measurements obtained using the test setup. The performance of this modification is evaluated over a sample set of devices. I.

The Linear Error Mechanism Modeling Algorithm (LEMMA has been developed with the aim of reducing test costs for DACs and ADCs, a particularly important class of mixed-signal integrated circuits. In this contribution, for the example of a 12-bit ADC, we report on the development and verification of LEMMA in an industrial production test environment. From the insight gained, we estimate the requirements and return-of-investment for higher resolution devices where traditional test techniques exhaust the time budget allowed for testing commodity parts.

This paper provides a review of the principles of chaotic digital communications using correlator receivers. Modulation schemes using one and two chaotic basis functions, as well as coherent and noncoherent correlation receivers, are discussed. The performance of differential chaos shift keying (DCSK) in multipath channels is characterized. Results are presented for DCSK with multiuser capability and multiple bits per symbol.

The application of the Linear Error Mechanism Modeling Algorithm (LEMMA) to various DAC and ADC architectures has raised the issue of including hard-fault-coverage as an integral part of the algorithm. In this work, we combine defect-oriented functionality tests and specification-oriented linearity tests of a mixed-signal IC to save test time. The key development is a novel test point selection strategy which not only optimizes the INL-prediction variance of the model, but also satisfies hard-fault-coverage constraints.

We propose a novel autonomous system for chaos generation based on a third-order abstract canonical mathematical model. Nonlinearity in this system is introduced by a bipolar switching constant which reflects the behaviour of a simple inverter circuit. Two implementations of the system are given. The first uses commercially available components while the second was designed on a CMOS chip. Numerical simulations and experimental results are provided.

The Frequency-Modulated Differential Chaos Shift Keying (FM-DCSK) modulation scheme offers a simple solution for wide-band communications applications such as indoor radio and Wireless Local Area Networks (WLAN). The main parameters of the telecommunications system have to be determined according to the special requirements of these applications. The most important system level parameters are the bandwidth of the channel filter, the bit duration, total radio frequency (RF) bandwidth of the transmitted signal and the Bit Error Rate (BER). This paper shows how these system level parameters have been determined for an FM-DCSK chaotic communications system which has been developed in the framework of a European Esprit project.

Double sampling phase-locked loop (2-SPLL) is used in frequency synthesis. The unique feature of single sampling PLL is that its phase detector (PD) has a very low unwanted periodic output in steady state. In 2-SPLL, a second sample and hold circuit (S&H) is connected in cascade to suppress further the unwanted periodic PD output. However, the absence of a proper baseband model and design equations prevent the exploitation of all benefits of 2-SPLL. This paper develops a nonlinear baseband model for the 2-SPLL. Then based on the linearized baseband model, analysis is performed in the frequency domain and the frequency responses required to determine the spectrum of the output signal as a function of reference and VCO noise and modulation inputs are developed. Finally, the theoretical results are verified by measurements.

Testing Analog-to-Digital Converters (ADCs) involves time-consuming measurements to estimate the location and spacing between the transition levels. From these measurements the Integral and Differential Nonlinearity (INL and DNL) are determined and cross-checked against the values given on the data sheet. The histogram test, an all-codes test, is widely used in industry. In this work, we compare for high-resolution ADCs this test method with a short-codes method that is based on combining the servo-loop setup and the LEMMA modeling technique. We demonstrate how and why the latter method outperforms histogramming in terms of test time.