Pushing physiological sensing into the wild: this work equips our ultra-low-power physiological BI-Vital sensor with an int8-quantized autoencoder that produces a real-time signal-quality index (SQI) for electrocardiograms (ECG) beside standard heart rate computations. The supervised model, trained on PhysioNet CinC2017 and three newly annotated BI-Vital single-lead ECG datasets, combines a compact encoder-decoder with a lightweight classifier head. On the STM32L476JE microcontroller from BI-Vital, the model uses 31 kB of RAM and 85 kB of flash memory, completes inference in 195 ms and still leaves room for parallel sensor services. Across eight train/test splits the approach generalizes well, reaching an F1 score of 0.988 while maintaining$2 \cdot 10^{-3}$performance loss after quantization. By converting raw continuous ECG data into periodic heart rate and SQI recordings, storage space on the device is reduced by 99.6%, demonstrating a practical way for reliable, data-efficient monitoring outside the laboratory.

Current discourse of communicative features of Asset Administration Shells (AAS) leaves an important aspect unaddressed: Should submodels be designed to be usable independently from their overarching AAS? Permitting such independent usage allows for more flexible physical deployment of individual AAS submodels in computer networks or on information media. In this paper, a presentation and classification of possible deployment variants is given, based on this principle. In addition, different requirements on the AAS infrastructure are discussed and how the deployment variants can contribute to their fulfillment. Finally, possible prioritization of infrastructure requirements and resulting submodel deployment are shown in three concrete usage scenarios.

Condition monitoring of unseen machines or operating conditions has received increasing attention in recent years. This study presents a computationally efficient approach to domain adaptation inspired by individual standardization for different subjects employed in EEG emotion recognition. On unseen working conditions, the individual standardization approach increases model performance by 15% for ROC and by 34% for accuracy, compared to models without domain adaptation. The approach achieves competitive scores without changing any other model parameters.

Engineering distributed control systems is a complex task, where the complexity and, thus, costs of the software development are growing rapidly. To keep the software complexity at an acceptable level and save time for development and subsequent maintenance, new solutions are sorely needed. In this paper, we investigate the advantages of using skills - universal control device interfaces - for generating complex logic in distributed control environments. By enriching a skill interface with the information about the dynamic behavior of a component under control, we compose the functionalities of individual control devices. The logic, required for such composition, is automatically derived from the interface description and the production plan, identifying the required skill sequence. The evaluation, executed using two industrial demonstrators, shows that the approach successfully handles different behavioral models and is capable of generating fault-tolerant orchestrators, including error handling scenarios. Overall, for developing a complex logic in a distributed skill-based automation system, the proposed approach shows significant savings in development time allowing to automate the skill composition task.

Modular automation is an upcoming paradigm to improve flexibility and maintainability of industrial production systems. The lack of interoperability between equipment adhering to different modular automation specifications limits module sourcing and hampers coexistence of discrete and process modules in joint hybrid production applications. In this work, we present a reference software architecture for modular automation which is able to cover existing specifications and demonstrate how it can be used to assess alternatives of cross-standard orchestration. Based on this foundation, next steps regarding cross-module and cross-orchestrator communication are outlined.

In the scope of Industry 4.0 (I40), one goal is the standardized access to asset information and asset services using standardized submodels (submodel templates) in the Asset Administration Shell. Since submodel templates are modeled by different groups of people, the same asset information will be contained in several submodel templates. For automatic generation of new submodels based on existing information from other submodels, model transformation can be a solution. Therefore, in this contribution, we present a guideline on how to develop a new model transformation language for a given use case and apply this guideline to the concrete use case (model transformation for Asset Administration Shells). As a result, we define of the abstract syntax of a customized model transformation language called AASMTL.

In multiprocessors, performance improvement is typically achieved by exploring parallelism with fixed granularities, such as instruction-level, task-level, or data-level parallelism. We introduce a new reconfiguration mechanism that facilitates variations in these granularities in order to optimize resource utilization in addition to performance improvements. Our reconfigurable multiprocessor QuadroCore combines the advantages of reconfigurability and parallel processing. In this article, a unified hardware-software approach for the design of our QuadroCore is presented. This design flow is enabled via compiler-driven reconfiguration which matches application-specific characteristics to a fixed set of architectural variations. A special reconfiguration mechanism has been developed that alters the architecture within a single clock cycle. The QuadroCore has been implemented on Xilinx XC2V6000 for functional validation and on UMC’s 90nm standard cell technology for performance estimation. A diverse set of applications have been mapped onto the reconfigurable multiprocessor to meet orthogonal performance characteristics in terms of time and power. Speedup measurements show a 2--11 times performance increase in comparison to a single processor. Additionally, the reconfiguration scheme has been applied to save power in data-parallel applications. Gate-level simulations have been performed to measure the power-performance trade-offs for two computationally complex applications. The power reports confirm that introducing this scheme of reconfiguration results in power savings in the range of 15--24%.

Timbre distance and similarity are expressions of the phenomenon that some music appears similar while other songs sound very different to us. The notion of genre is often used to categorize music, but songs from a single genre do not necessarily sound similar and vice versa. In this work, we analyze and compare a large amount of different audio features and psychoacoustic variants thereof for the purpose of modeling timbre distance. The sound of polyphonic music is commonly described by extracting audio features on short time windows during which the sound is assumed to be stationary. The resulting down sampled time series are aggregated to form a high-level feature vector describing the music. We generated high-level features by systematically applying static and temporal statistics for aggregation. The temporal structure of features in particular has previously been largely neglected. A novel supervised feature selection method is applied to the huge set of possible features. The distances of the selected feature correspond to timbre differences in music. The features show few redundancies and have high potential for explaining possible clusters. They outperform seven other previously proposed feature sets on several datasets with respect to the separation of the known groups of timbrally different music.

Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. Since the extension of an instruction set and its utilization are non-trivial tasks, sophisticated tools have to provide guidance and support during design. Feedback driven optimization allows for the highest level of specialization, but calls for a simulator that is aware of the newly proposed instructions, a compiler that makes use of these instructions without manual intervention, and an application program that is representative for the targeted application domain.In this paper we introduce an approach for the extension of instruction sets that is built around a concise yet powerful processor abstraction. The specification of a processor is well suited to automatically generate the important parts of a compiler backend and cycle-accurate simulator. A typical design cycle involves the execution of the representative application program, evaluation of performance statistics collected by the simulator, refinement of the processor specification guided by performance statistics, and update of the compiler and simulator according to the refined specification. We demonstrate the usefulness of our novel approach by example of an instruction set for symmetric ciphers.

The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, evaluation, and realization of a parameterizable network processing unit. In this paper we present a design methodology for network processors which encompasses the research areas from the application software down to the gate level of the chip. Key components of this holistic approach have been successfully applied to characteristic examples of architecture refinements.

In this paper, we present an efficient exploration algorithm for architecture/compiler co-designs of application-specific instruction-set processors. The huge design space is spanned by processor architecture parameters as well as different compiler optimization strategies. The objective space is multi-dimensional including conflicting objectives such as hardware cost, execution time and code size. The goal of the presented exploration algorithm is to determine the set of Pareto-optimal designs and compiler settings for a given benchmark program. In a case study, while exploring Pareto-optimal designs for a given DSP benchmark program, we show that for a realistic architecture family, the huge search space may be reduced dramatically using proper techniques to prune search spaces that may not contain Pareto-optimal solutions. Finally, we analyse and present solutions on what is the best architecture for a mixture of benchmark programs, i.e., what are the best architecture/compiler co-designs to execute the DSPstone benchmark.

In the design of application-specific instruction set processors (ASIPs) a tight interplay between architecture and compiler is of utmost importance. Here, we try to characterize the design space of both compiler frontend (intermediate code optimization) and backend (architecture-specific code generation) that is used in order to do Architecture/Compiler Co-Exploration for the search of optimal architecture/compiler combinations. The described results present the state of development of such a framework called BUILDABONG [3].