Shape representation is a major challenge in machine perception, and is the basis for vision. Most current theories of shape representation are based on the idea of feature or part extraction. Compared with template matching and Fourier decomposition, parts-based mechanism is better adapted to the real-world difficulties of view-point transformations, partial occlusion and plastic deformation. We present in this paper a parts-based shape representation model inspired by the mammalian visual ventral pathway. With the sparse coding constraint, the computational model combines unsupervised representation in the feed-forward stream with lateral interaction to achieve stable, efficient and natural representation of shapes. Further comparing the response properties of model cells to those of biological V4 cells, we find that model cells display same curvature and object centered tuning as the reported physiological measurements.

We investigate the effectiveness of a financial time-series forecasting strategy which exploits the multiresolution property of the wavelet transform. A financial series is decomposed into an over complete, shift invariant scale-related representation. In transform space, each individual wavelet series is modeled by a separate multilayer perceptron (MLP). We apply the Bayesian method of automatic relevance determination to choose short past windows (short-term history) for the inputs to the MLPs at lower scales and long past windows (long-term history) at higher scales. To form the overall forecast, the individual forecasts are then recombined by the linear reconstruction property of the inverse transform with the chosen autocorrelation shell representation, or by another perceptron which learns the weight of each scale in the prediction of the original time series. The forecast results are then passed to a money management system to generate trades.

The adaptive-subspace self-organizing map (ASSOM) proposed by Kohonen is a recent development in self-organizing map (SOM) computation. In this paper, we propose a method to realize ASSOM using a neural learning algorithm in nonlinear autoencoder networks. Our method has the advantage of numerical stability. We have applied our ASSOM model to build a modular classification system for handwritten digit recognition. Ten ASSOM modules are used to capture different features in the ten classes of digits. When a test digit is presented to all the modules, each module provides a reconstructed pattern and the system outputs a class label by comparing the ten reconstruction errors. Our experiments show promising results. For relatively small size modules, the classification accuracy reaches 99.3% on the training set and over 97% on the testing set.

Adiabatic logic promises extremely low power consumption for those applications where slower clock rates are acceptable. However, there have been very few adiabatic memory designs, and any circuit of even moderate complexity requires some form of RAM. This paper presents a register file implemented entirely with adiabatic logic, and fabricated using a 1.2 µm CMOS technology. Comparison with a conventional CMOS logic implementation, using both measured and simulated results, indicates significant power savings have been realised.

We describe in this paper a novel approach based upon machine learning for estimating layout shape functions of full-custom integrated circuit cells. A neural network is trained to estimate one dimension of cell layout from circuit netlist, a desired packing density, and prescribed values of the complementary dimension. The neural network is then combined with a linear function generator and a neural network that predicts the number of contacts (vias) to produce estimates of cell layout shape functions. We have experimented with this approach on an independent test set of circuits and the results are very encouraging. The resulting estimation system is very fast and can be easily incorporated into exiting floorplanning systems. An additional benefit of the the machine learning aspect is the simplicity and systematicity in incorporating into the estimation system new circuits and technology information as they become available.

The estimation of the height and width of a custom cell layout (CCL) from schematics is an important task in integrated circuit computer aided design and can be of direct assistance to designers. In this paper, we describe and report results on two CCL dimension estimation techniques. In the first, a neural network is trained to predict the width (or height) of a cell given its schematics and its height (or width). The results show that knowledge of one dimension significantly improves the prediction accuracy of the other. In the second, we explore improvements to previous work (see IEEE Trans. on Neural Networks, vol. 3, no. 1, p. 146-153, 1992) on simultaneous CCL dimension prediction by replacing the neural network that estimates the width and height simultaneously by cascaded neural networks.

The design, implementation, and operation of a low-power multilayer perceptron chip (Kakadu) in the framework of a cardiac arrhythmia classification system is presented in this paper. This classifier, called MATIC, makes timing decisions using a decision tree, and a neural network is used to identify heartbeats with abnormal morphologies. This classifier was designed to be suitable for use in implantable devices and a VLSI (very large scale integration) neural-network chip (Kakadu) was designed so that the computationally expensive neural-network algorithm can be implemented with low power consumption. Kakadu implements a (10,6,4) perceptron and has a typical power consumption of tens of microwatts. When used with the arrhythmia classification system, the chip can operate with an average power consumption of less than 25 nW.

An analogue VLSI neural network has been designed and tested to perform cardiac morphology classification tasks. Analogue tech(cid:173) niques were chosen to meet the strict power and area requirements of an Implantable Cardioverter Defibrillator (ICD) system. The ro(cid:173) bustness of the neural network architecture reduces the impact of noise, drift and offsets inherent in analogue approaches. The net(cid:173) work is a 10:6:3 multi-layer percept ron with on chip digital weight storage, a bucket brigade input to feed the Intracardiac Electro(cid:173) gram (ICEG) to the network and has a winner take all circuit at the output. The network was trained in loop and included a commercial ICD in the signal processing path. The system has suc(cid:173) cessfully distinguished arrhythmia for different patients with better than 90% true positive and true negative detections for dangerous rhythms which cannot be detected by present ICDs. The chip was implemented in 1.2um CMOS and consumes less than 200n W max(cid:173) imum average power in an area of 2.2 x 2.2mm2.

The TNM staging system has been used since the early 1960's to predict breast cancer patient outcome. In an attempt to in(cid:173) crease prognostic accuracy, many putative prognostic factors have been identified. Because the TNM stage model can not accom(cid:173) modate these new factors, the proliferation of factors in breast cancer has lead to clinical confusion. What is required is a new computerized prognostic system that can test putative prognostic factors and integrate the predictive factors with the TNM vari(cid:173) ables in order to increase prognostic accuracy. Using the area un(cid:173) der the curve of the receiver operating characteristic, we compare the accuracy of the following predictive models in terms of five year breast cancer-specific survival: pTNM staging system, princi(cid:173) pal component analysis, classification and regression trees, logistic regression, cascade correlation neural network, conjugate gradient descent neural, probabilistic neural network, and backpropagation neural network. Several statistical models are significantly more ac-

An analogue neural network VLSI chip designed for low power operation is presented. This chip consists of 84 synapse elements arranged as arrays of size 10 x 6 and 6 x 4 and was fabricated using a standard 1.2 micron double metal single poly CMOS process. The synapses are digitally programmable and static weight storage is provided. The chip has a typical power consumption of tens of microwatts. It has been successfully trained and tested on a range of classification problems including 4-bit parity, character recognition and morphological-based classification of intracardiac electrogram signals.

A clock routing scheme that guarantees a zero-skew routing result is proposed. It is shown that the time complexity for the algorithm can be reduced to O(n/sup 2/ log n) by using the modified Voronoi diagram to structure the algorithm. L-shaped pairing and H-flipping operations are introduced to further reduce the clock wire length. Extensions are made to the algorithm for use in building-block layout and zero skew is also achieved. Significant reduction in total clock wire lengths is observed.>

Previous work on analog VLSI implementation of multilayer perceptrons with on-chip learning has mainly targeted the implementation of algorithms such as back-propagation. Although back-propagation is efficient, its implementation in analog VLSI requires excessive computational hardware. It is shown that using gradient descent with direct approximation of the gradient instead of back-propagation is more economical for parallel analog implementations. It is shown that this technique (which is called ;weight perturbation') is suitable for multilayer recurrent networks as well. A discrete level analog implementation showing the training of an XOR network as an example is presented.

A statistical quantization model is used to analyze the effects of quantization when digital techniques are used to implement a real-valued feedforward multilayer neural network. In this process, a parameter called the effective nonlinearity coefficient, which is important in the studying of quantization effects, is introduced. General statistical formulations of the performance degradation of the neural network caused by quantization are developed as functions of the quantization parameters. The formulations predict that the network's performance degradation gets worse when the number of bits is decreased; that a change of the number of hidden units in a layer has no effect on the degradation; that for a constant effective nonlinearity coefficient and number of bits, an increase in the number of layers leads to worse performance degradation; and the number of bits in successive layers can be reduced if the neurons of the lower layer are nonlinear.

Previous work on analog VLSI implementation of multilayer perceptrons with on-chip learning has mainly targeted the implementation of algorithms like backpropagation. Although backpropagation is efficient, its implementation in analog VLSI requires excessive computational hardware. In this paper we show that, for analog parallel implementations, the use of gradient descent with direct approximation of the gradient using "weight perturbation" instead of backpropagation significantly reduces hardware complexity. Gradient descent by weight perturbation eliminates the need for derivative and bidirectional circuits for on-chip learning, and access to the output states of neurons in hidden layers for off-chip learning. We also show that weight perturbation can be used to implement recurrent networks. A discrete level analog implementation showing the training of an XOR network as an example is described.

Article Free Access Share on BREL—a Prolog knowledge-based system shell for VLSI CAD Author: Marwan A. Jabri Systems Engineering and Design Automation Laboratory (SEDAL), Sydney University Electrical Engineering, NSW 2006 Australia Systems Engineering and Design Automation Laboratory (SEDAL), Sydney University Electrical Engineering, NSW 2006 AustraliaView Profile Authors Info & Claims DAC '90: Proceedings of the 27th ACM/IEEE Design Automation ConferenceJanuary 1991 Pages 272–277https://doi.org/10.1145/123186.123273Online:03 January 1991Publication History 4citation213DownloadsMetricsTotal Citations4Total Downloads213Last 12 Months4Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Article Free Access Share on PIAF: a knowledge-based/algorithm top-down floorplanning system Authors: M. A. Jabri Systems Engineering and Design Automation Laboratory, Sydney Univewity Electrical Engineering, NSW 2006 Australia Systems Engineering and Design Automation Laboratory, Sydney Univewity Electrical Engineering, NSW 2006 AustraliaView Profile , D. J. Skellern Systems Engineering and Design Automation Laboratory, Sydney Univewity Electrical Engineering, NSW 2006 Australia Systems Engineering and Design Automation Laboratory, Sydney Univewity Electrical Engineering, NSW 2006 AustraliaView Profile Authors Info & Claims DAC '89: Proceedings of the 26th ACM/IEEE Design Automation ConferenceJune 1989 Pages 582–585https://doi.org/10.1145/74382.74480Published:01 June 1989Publication History 6citation157DownloadsMetricsTotal Citations6Total Downloads157Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The authors describe the design and implementation of an application-specific integrated circuit (ASIC) for multichannel formant speech synthesis. The primary objective was to develop an efficient bit-serial VLSI structure with sufficient acoustical and processing performance for high-quality, intelligible, multichannel synthetic speech production. Functional design was performed using the Denyer/Renshaw FIRST Silicon compiler. The implementation of a technology-independent FIRST bit-serial primitive operator library using the MODEL hardware description language is also described. This library has been implemented on a European Silicon Structures (ES2) SOLO-1000 Standard cell design tool and has been used to design the device.>