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Demo Data from EDBT 2026 / reviewers in the wild / expert

Nancy Nettleton

dblp:64/2522 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 77% Integrated circuit design · 23%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › CAD framework
design tool interoperability		 0.012002
Tools or users: which is the bigger bottleneck? · DAC 2002
Electronic design automation
design methodology		 0.012001
Panel: Is Nanometer Design Under Control? · DAC 2001
Integrated circuit design › VLSI design
nanometer-scale integrated circuit design		 0.012001
Panel: Is Nanometer Design Under Control? · DAC 2001
YearPublicationVenuePosition
2002 Tools or users: which is the bigger bottleneck?
abstract
As chip design becomes ever more complex, fewer design teams are succeeding. Who's to blame? On one hand, tools are hard to use, buggy, not interoperable, and have missing functionality. On the other hand, there is a wide range of engineering skills within the user population, and tools can be abused within flawed methodologies. This panel will quantify and prioritize the key gaps, including interoperability, that must be addressed on both sides.
Andrew B. Kahng, Ronald Collett, Patrick Groeneveld, Lavi Lev, Nancy Nettleton, Paul K. Rodman, Lambert van den Hoven
 DAC5
2001 Panel: Is Nanometer Design Under Control?
abstract
As fabrication technology moves to 100 nm and below, profound nanometer effects become critical in developing silicon chips with hundreds of millions of transistors. Both EDA suppliers and system houses have been re- tooling, and new methodologies have been emerging. Will these efforts meet the challenges of nanometer silicon such as performance closure, power, reliability, manufacturability, and cost? Which aspects of nanometer design are, or are not, under control? This session will consist of a debate between two teams of distinguished representatives from EDA suppliers and system design houses. Which side has the right answers and roadmap? You and a panel of judges will decide!
Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis K. Scheffer, Ed Cheng, Sang Wang
 DAC3
2001 Differences in ASIC, COT and processor design (panel)
abstract
No abstract available.
Nancy Nettleton, Wolfgang Roethig, D. Hill, Majid Sarrafzadeh
 ISPD1