Mini/Micro LEDs are becoming the next generation of displays, with sizes shrinking to less than 100μm/50μm and integration scaling increasing by more than 100-fold. Fast and precise sorting, which includes the identification and localization of mass mini/micro LED chips, has become an urgent need in the industry due to its high efficiency and reliability. However, the small size, high density, and weak defects of the mini/micro LED, combined with the industrial rapid sorting requirement, pose challenges to the sorting task. To address these issues, we propose a fast and precise visual sorting approach that includes accurate chip identification and pixel-level localization. In detail, a double-ended self-attention (SA) encoder–decoder hybrid convolutional encoder neural network framework is designed to accommodate both local features and global information. Then, two generic patch enhancement modules are constructed to compensate for the local feature modeling inefficiencies inherent in SA. Finally, the light SA encoder (Li-SA Co) and light SA covariance decoder (Li-SA-Cov Dec) basic blocks are proposed to speed up sorting. The effectiveness of the proposed approach is demonstrated by the actual mini/micro LED industrial images acquired, which have an mAP of 97.1%, a localization success of 98.6%, and a speed of 20.1FPS, all of which are higher than those of other state-of-the-art methods.

An ultralow quiescent current dc-dc buck converter based on adaptive on-time (AOT) control is presented in this article. To minimize the energy wastage of the dc-dc buck converter circuit when the Internet-of-Things (IoT) device is in standby mode, a control loop with nano-ampere quiescent current is proposed in this converter. To reduce the quiescent current consumed by the voltage reference and improve its line sensitivity (LS), the voltage reference in the proposed converter is preregulated and based on the subthreshold CMOS implementation, with a quiescent current of only 20 nA. Meanwhile, for purpose of maintaining high efficiency of the converter under the ultralow load, an adaptive comparator based on the dynamic bias mode selection circuit is proposed, which converts the load conditions into time information and switches the bias current and gain of the comparator under ultralow loads, and the quiescent current of the comparator is only 65 nA. The proposed converter is implemented in a 0.18-$\mu $m BCD process with an area of 1.35 mm2. Experimental results show that the converter has a minimum quiescent current of 285 nA, maintains more than 80% conversion efficiency over a load range of$10~\mu $A–300 mA and a peak efficiency of 94.7%, and has an output of 0.9–4.8 V over a supply condition of 2–5.5 V.

This paper presents a 13-tap FIR filter and an IIR filter embedded in a 10-bit SAR ADC for wireless communications chip. The IIR filter can be inherently realized through reusing the capacitor array of the SAR ADC, thus improving the stopband suppression and shaping the transition band. Besides, the DC attenuation is also avoided. The sampling rate loss of the SAR ADC can be compensated by the$4\times $time-interleaving technology. The proposed filter features high power-efficient, linearity and process compatibility. Compared with a 15-tap FIR filter, the out-of-band suppression at the cut-off frequency (OOBS@$f_{\mathrm {cut-off}}$) is enhanced by 9dB theoretically. A prototype FIR/IIR filter in 40nm CMOS occupies an active area of 0.067mm2, consumes$38~\mu \text{W}$at a single supply of 1.1V, has a 1-MHz bandwidth, obtains$>$42.2dB [email protected] when operated at 40MS/s. Meanwhile, the SAR ADC without/with the proposed filter can achieve a FoMw of 7.91 fJ/conversion-step and 13.5 fJ/conversion-step, respectively.

In this letter, we present an attentional non-linear activation function approximation method called ATA for VLSI-based neural networks. Unlike other approximation methods that pursue the low hardware resources with a high recognition accuracy loss, the ATA utilizes the pixel attention to focus on the important features to keep the recognition accuracy and reduce resource cost. Specifically, attention applied in the activation function is realized by the approximated activation functions with different fitting errors for VLSI-based neural networks. The important features are highlighted by the piecewise linear function and improved look-up table with low fitting error, while the trivial features are ignored with the large fitting error. Experimental results demonstrate that the ATA outperforms other state-of-the-art approximation methods in recognition accuracy, power and area.

In this paper, a methodology based on the cost of bus throughput, transmission latency and power consumption is proposed to achieve integrated optimization of NoC topology modeling and generation. The optimized framework's static and dynamic properties ensure efficient core-to-core communication of the complete network. Our approach 1) fully exploits the regularity of standard topology and the flexibility of application-specific topology 2) generates a scalable network containing heterogeneous topologies, which raises the abstraction level of reuse from resources to subnets 3) satisfies NoC application. The performances of the topology are simulated and compared between the proposed methodology and regular NoC topologies, including mesh and optimal mesh architecture. Experimental results show the proposed design flow is efficient to provide better performance for predefined requirements, and minimal cost function is achieved. In addition, we applied several multimedia applications as case studies.

Shrinking transistor sizes and recent trends toward many-core chips have heightened the need for an efficient on-chip communication network to integrate various cores. However, buses and point-to-point interconnection will not result in scalability, modularity, and explicit parallelism, as well as may suffer great performance bottleneck. While state-of-art packet-switched network increases the communication costs and is incapable of performing multicast service. In addition, the emergence of reconfigurable system needs a flexible and application-specific architecture which could dynamically customize the systems. HCR-NoC (Hybrid-Communication Reconfigurable Network-on-Chip) is proposed in this paper, which could dynamically reconfigure MPSoC architecture based on buses traffic. To satisfy different communication services, we use a TDMA shared bus for inter-cluster communication in a designable framework, which enables topology reconfiguration upon regular physical network topology. An analytical verification tool is presented to simulate HCR-NoC system performance. Finally, the evaluations of HCR-NoC using Multimedia benchmarks show that significant reduction in power and area as compared to optimal mesh architecture NoC.

High complexity of frequency-hopping (FH)/spread-spectrum (SS) sequence is of great importance to high-security multiple-access communication systems, for it makes FH/SS sequence difficult to be analyzed. With the growing development in the design of FH/SS sequence in much wider fields, the well-known complexity measures - the linear complexity (LC), the linear complexity profile (LCP) and the k-error linear complexity (k-error LC) - are widely used but not sufficient to evaluate the complexities of the sequences available, such as the cryptographical sequence and the chaotic sequence families. In this paper, a new complexity metric to evaluate the unpredictability of FH/SS sequence based on the approximate entropy (ApEn) is proposed in the view of the maximal randomness of the sequences with arbitrary length. And the theoretical bounds of the ApEn are derived from a probabilistic point of view. Simulations and analysis results show that, the proposed ApEn works effectively to discern the changing complexities of the FH/SS sequences with small number of samples, which provide superior performance over its candidates.

High complexity of frequency-hopping (FH)/spread-spectrum (SS) sequence is of great importance to high-security multiple-access communication systems, for it makes FH/SS sequence difficult to be analyzed. With the growing development in the design of FH/SS sequence in much wider fields, the well-known complexity measures-the linear complexity (LC), the linear complexity profile (LCP) and the k-error linear complexity (k-error LC)-are widely used but not sufficient to evaluate the complexities of the sequences available, such as the cryptographical sequence and the chaotic sequence families. In this paper, a new complexity metric to evaluate the unpredictability of FH/SS sequence based on the approximate entropy (ApEn) is proposed in the view of the maximal randomness of the sequences with arbitrary length. And the theoretical bounds of the ApEn are derived from a probabilistic point of view. Simulations and analysis results show that, the proposed ApEn works effectively to discern the changing complexities of the FH/SS sequences with small number of samples, which provide superior performance over its candidates.

High complexity of frequency-hopping (FH)/spreadspectrum (SS) sequence is of great importance to high-security multiple-access communication systems, for it makes FH/SS sequence difficult to be analyzed. With the growing development in the design of FH/SS sequence in much wider fields, the wellknown complexity measuresiquestthe linear complexity (LC), the linear complexity profile (LCP) and the k-error linear complexity (k-error LC)iquestare widely used but not sufficient to evaluate the complexities of the sequences available, such as the cryptographical sequence and the chaotic sequence families. In this paper, a new complexity metric to evaluate the unpredictability of FH/SS sequence based on the approximate entropy (ApEn) is proposed in the view of the maximal randomness of the sequences with arbitrary length. And the theoretical bounds of the ApEn are derived from a probabilistic point of view. Simulations and analysis results show that, the proposed ApEn works effectively to discern the changing complexities of the FH/SS sequences with small number of samples, which provide superior performance over its candidates.

Spatial subchannels in multiuser multiple-input multiple-output/orthogonal frequency-division multiplexing (MIMO/OFDM) systems are invested. With the goal of maximizing the overall system throughput, we derive the criterion of subcarrier allocation and introduce an adaptive resource allocation algorithm. Furthermore, a time-frequency blockwise loading design which may decrease the computational complexity is suggested. The simulation results show that the algorithm can achieve good performance and high transmission rate efficiently.

According to the analysis of MBC (meteor burst communication) mechanism, a model of signal processing based on the structure of data frame is suggested for adaptive modulation and coding (AMC) of MBC system in this paper. There are two distinct modes of operation for signal processing: acquisition and tracking. The acquisition mode is a training period to initialize the channel estimation by frame header. The tracking mode is jointly to equalize payload data and to trace channel, where the principle of per-survivor processing (PSP) for maximum likelihood sequence detection (MLSD) is performed. A suboptimal method called D-PSP is adopted to save the computational time and memory size, which agrees with the slow-fading characteristic of meteor channel and makes the MLSD possible for adaptive modulation and coding of MBC system. Computer simulation results are included to support our development