Efficient and flexible Viterbi decoding is an important problem in implementation of modern telecommunications systems. In this paper, a 256-state, rate 1/2 Viterbi decoder is implemented on a transport triggered architecture processor. Due to the processor-based platform, the implementation is flexible and it can achieve relatively high decoding speed. The decoder is implemented by tailoring the processor to meet the requirements of Viterbi decoding. The processor is enhanced with a number of special function units, which accelerate the decoding. As a result, the decoding can be carried out efficiently on a processor-based platform.

A systematic approach for the path metric memory management in Viterbi decoders is presented. Between the parallel computation units and memory modules, a permutation of path metrics is required in order to access the path metrics in correct order. We propose a parallel memory access scheme, which reduces the interconnection complexity between parallel computation units and memory modules by rescheduling the path metric computations.

We consider a multicarrier code-division multiple access (MC-CDMA) system over multipath fading channels. We first develop a model for such a system. Then, we propose the channel estimation based on least square (LS) algorithm and linear interpolation in frequency domain. For signal detection, different detection algorithms are introduced including maximum ratio combining (MRC), minimum mean square error (MMSE), parallel interference cancellation (PIC), and interference cancellation based on expectation-maximization (EM) algorithm. Performances of these different algorithms are illustrated by numerical results in a system with 512 subcarriers and 5 MHz bandwidth at 2.5 GHz over some of ITU channel models. Our simulation results demonstrate that with MMSE algorithm significant performance gain is achieved compared to that with MRC algorithm. The system performance can be further improved by PIC and EM algorithms.

The computational requirements of turbo decoders are heavy and depend on the number of decoding iterations. However, only a few iterations are often enough for obtaining an error free outcome. Instead of idling during the unused iterations, the released time slots can be used for enabling extra iterations required by the decoding, when the errors are more severe. Since the number of required iterations for each code block is not known beforehand, the allocation of iterations must adapt according to the current demand and the past iterations. In this paper, the dynamic adaptation is achieved by an additional buffering of incoming code blocks and the effect of utilizing unused iterations are studied.

The memory requirements of turbo decoders are high since long code block lengths are preferred. Especially, the extrinsic information memory is accessed frequently with both linear and interleaved access patterns. In this paper, a parallel access scheme into extrinsic information memory is developed for a 3GPP turbo decoder. A single port memory is divided into parallel accessible modules and the memory throughput requirements and both the linear and interleaved access patterns are considered as module and word address generating functions are developed. As a result, the throughput of the parallel access scheme allows high-speed decoding and the usage of the dual port memory can be avoided and savings in chip area are achieved.