Current main memory organizations in embedded and mobile application systems are DRAM dominated. The ever-increasing gap between today's processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design. However, the limitations to DRAM scaling and other challenges like refresh provide undesired trade-offs between performance, energy and area to be made by architecture designers. Several emerging NVM options are being explored to at least partly remedy this but today it is very hard to assess the viability of these proposals because the simulations are not fully based on realistic assumptions on the NVM memory technologies and on the system architecture level. In this paper, we propose to use realistic, calibrated STT-MRAM models and a well calibrated cross-layer simulation and exploration framework, named SEAT, to better consider technologies aspects and architecture constraints. We will focus on general purpose/mobile SoC multi-core architectures. We will highlight results for a number of relevant benchmarks, representatives of numerous applications based on actual system architecture. The most energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 27% at the cost of 2x the area and the least energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 8% at the around the same area or lesser when compared to DRAM.

SRAM based memory systems are plagued by a number of problems like sub-threshold leakage and susceptibility to read/write failure with dynamic voltage scaling schemes or low supply voltage. Non-Volatile Memory (NVM) technologies are being explored extensively nowadays to replace the conventional SRAM memories even for level 1 (L1) caches. These NVMs like Spin Torque Transfer RAM (STT-MRAM), Resistive-RAM (ReRAM) and Phase Change RAM (PRAM) are less hindered by leakage problems with technology scaling and consume lesser area. However, simple replacement of SRAM by NVMs is not a viable option due to their write related issues. The main focus of this paper is the exploration of write delay and write energy issues in a NVM based L1 Instruction cache (I-cache) for an ARM like single core system. We propose a NVM I-cache and extend its MSHR (Miss Status Handling Register) functionality to address the NVMs write related issues. According to our simulations, appropriate tuning of selective architecture parameters can reduce the performance penalty introduced by the NVM (∼45%) to extremely tolerable levels (∼1%) and show energy gains up to 35%. Furthermore, on configuring our modified NVM based system to occupy area comparable to the original SRAM-based configuration, it outperforms the SRAM baseline and leads to even more energy savings.

Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising non-volatile memory technologies and shows potential as an SRAM replacement. However, targeted for advanced CMOS technologies such as the 14nm FinFET node, time-zero variability is a major concern for these memory technologies. In this paper, we investigate the STT-MRAM variability with respect to different technology scenarios. We show the impact of these variations on the bit error rate of the emerging STT-MRAM memories.

Recently, Software Defined Networking (SDN) has gained a lot of attention, even for the use in core communication networks. When deploying SDN in large core networks, the number and location of controllers must be carefully planned. A first study on this topic by Heller et al. [3] was followed by more detailed publications that included resilience or dynamic controller provisioning. In our previous work [2], we provide an overview over related work and include different resilience issues in the controller placement process. We argued that it is not sufficient to look only at node-to-controller latencies but a controller placement should also fulfill certain resilience constraints especially for the control plane.

We present a systematic methodology for exploring application partitioning and assignment together with platform architecture instantiation. Streaming applications with multiple runtime modes are considered. The platform architecture is based on a domain specific MPSoC architecture template. We show results using complete inner modem physical layer processing of wireless applications, WLAN and LTE. We show that the proposed methodology obtains up to 30% energy improvement in energy with negligible area overheads as compared to straight-forward mapping to one processor, while meeting performance constraints, for a multi-mode WLAN 11n system and single-mode LTE system.

Recently, multiple non-volatile emerging memories (NVMs) have been proposed and show promising properties to replace SRAM-based memories in future SoCs. However, these new emerging memories, such as STT-MRAM and ReRAM, provide new challenges for the processor design e.g. larger write latencies, higher power and lower endurance. In this paper, we propose a design method for memristor-based (ReRAM) memory architectures for embedded processors to address the effects caused by longer write latencies. We evaluate this method and present the design space for using ReRAM in the data memory of an wireless base band processor. We propose architectural solutions for concealing the slow write speed of ReRAM and show their trade-offs in terms of performance with respect to different write latencies. We show that for single benchmarks the performance penalty caused by the ReRAM write latency can be reduced to 7% for the complete wireless communication benchmark suite. Morevoer, for single benchmarks the performance penalty can be eliminated completely.

Recent developments in network science will facilitate the Internet as we know it today to integrate existing and upcoming technologies into a heterogeneous and highly dynamic resource pool. This enables the design of new applications and services which will form the Future Internet (FI). From this, many interesting prospects and unknown flexibility in terms of resource usage arise. In order to achieve this flexibility and make it usable for Service Providers (SPs) a key concept of the FI will be Virtual Networks (VNs) embedded into this resource pool. Furthermore, Federation which includes a closer interaction, resource sharing, and information exchange between providers will be an enabler for this freedom of design. This allows the operation of heterogeneous and divergent services on the same physical infrastructure substrate. It is clear to see that all these upcoming possibilities offer new areas of research. In this work we structure the parameters required to describe resources and services accurately. Furthermore, we summarize research questions that need to be resolved in order to make the FI a story of success.

The rapidly evolving and diversifying wireless landscape demands highly flexible wireless chipsets. Due to the ultimate programmability, SDR solutions are becoming more and more attractive. However, the programmability overhead is still a concern for the silicon area cost of SDR solutions. In this work, we prove that, with algorithm and architecture co- design, SDR solutions can be very competitive even when compared to highly optimized ASICs. Specifically, we show a baseband processor design that can support ISDB-T, DVB-T and ATSC, but the area cost is still comparable to the combination of ASICs which handle the three terrestrial digital TV standards respectively.

With the soaring development cost of deep sub-micron silicon and the fast-growing diversity in wireless communications, software defined baseband becomes more and more important for handheld devices. However, most software defined receivers reported in previous literatures are still far away from fulfilling the requirement of emerging wireless standards such as the LTE-Advanced. The category-E User Equipment (UE) defined in LTE-Advanced, as the most demanding category for handheld devices, requires processing 2 concurrent data streams at around 300Mbps aggregated throughput. It is not clear whether SDR baseband processors can tackle this challenge. In our work, we explore the feasibility for software defined baseband for LTE-Advanced. With a highly customized SDR baseband processor, we have recently accomplished a software defined downlink inner receiver for Category-E LTE-Advanced UE. The implemented inner receiver includes fully fledged synchronization and data detection functionalities, including coarse CFO estimation/compensation, I/Q imbalance estimation/compensation, OFDMA demodulation, channel estimation, fine SCO/CFO estimation/compensation, MIMO channel processing, MIMO data detection and LLR generation. This paper is intended to bring an overview for the work and emphasizes key aspects that enable the feasibility of the work. In this paper, we will introduce the algorithm and processor architecture co-design flow, overall receiver functionalities, important optimizations and implementation results.

Intradomain routing in IP networks follows shortest paths according to administrative link costs. When several equal-cost shortest paths exist, routers that use equal-cost multipath (ECMP) distribute the traffic over all of them. To produce single-shortest path (SSP) routing, a selection mechanism (tie-breaker) chooses just one of the equal-cost paths. Tie-breakers are poorly standardized and use information that may change over time, which makes SSP routing unpredictable. Therefore, link costs producing unique shortest paths (USP) are preferred. In this paper, we show that optimized SSP routing can lead to significantly higher link utilization than expected in case of non-deterministic tie-breakers. We investigate the impact of the allowed link cost range on the general availability of USP routing. We use a heuristic algorithm to generate link costs for USP routing and to minimize the maximum link utilization in networks with and without failures. Fast reroute (FRR) mechanisms can repair failures faster than conventional IP rerouting by pre-computing shortest backup paths around failed network elements. However, when multiple equal-cost paths exist, the backup path layout is unpredictable. We adapt our heuristic to optimize USP routing for IP-FRR using not-via addresses and MPLS-FRR with facility and one-to-one backup. Finally, we compare the performance of USP with various other routing schemes using realistic Rocket-fuel topologies.

The locator/identifier split is a design principle for new routing architectures that make Internet routing more scalable. To find the location of a host, it requires a mapping system that returns appropriate locators in response to map-requests for specific identifiers. In this paper, we propose FIRMS, a "Future Internet Routing Mapping System". It is fast, scalable, reliable, secure, and it is able to relay initial packets. We introduce its design, show how it deals with partial failures, explain its security concept, and evaluate its scalability.

Multi-topology routing is an increasingly popular IP network management concept that allows transport of different traffic types over disjoint network paths. The concept is of particular interest for implementation of IP fast reroute (IP FRR). The authors have previously proposed an IP FRR scheme based on multi-topology routing called Multiple Routing Configurations (MRC). MRC supports guaranteed, instantaneous recovery from any single link or node failure in biconnected networks as well as from many combined failures, provided sufficient bandwidth on the surviving links. Furthermore, in MRC different failures result in routing over different network topologies, which gives a good control of the traffic distribution in the networks after a failure

Multi-topology routing is an increasingly popular IP network management concept that allows transport of different traffic types over disjoint network paths. The concept is of particular interest for implementation of IP fast reroute (IP FRR). First, it can support guaranteed, instantaneous recovery from any link or node failure. Second, different failures result in routing over different network topologies, which augments the parameter space for load distribution optimizations. Multiple routing configurations (MRC) is the state-of-the-art IP FRR scheme based on multi-topology routing today. In this paper we present a new, enhanced IP FRR scheme which we call ldquorelaxed MRCrdquo (rMRC). rMRC simplifies the topology construction and increases the routing flexibility in each topology. According to our experimental evaluation, rMRC has several benefits compared to MRC. The number of backup topologies required to provide protection against the same set of failures is reduced, hence reducing state in routers. In addition, the backup paths are shorter, and the link utilization is significantly better.