A novel mixed-signal adaptable silicon-based coherent photoacoustic (PA) sensing system-on-chip (SoC) is proposed to detect various kinds of target signals robustly under high noise and strong interferences in compact chip-level, attaining precise in vivo sensing for physiological signs monitoring and enhanced bio-imaging. Based on the configurable coherent PA sensing SoC architecture supported by on-chip Gilbert cell-based multiplier, a digital processing module, and DACs, in-phase (I) and quadrature (Q) templates generated by digital module on-chip are configurable to be with a high correlation coefficient to the target PA signal, attaining detection and reconstruction of target signals in a coherent detection mode. The correlation between the received PA signal and the templates is implemented efficiently, assuring accurate tracking and precise reconstruction on the target PA signals at the chip level. Based on the integrated PA SoC fabricated by the TSMC 65-nm CMOS process, precise in vivo sensing and imaging can be assured at the edge. Further, as PA detection leverages optical and ultrasound sensing, in vivo imaging on in-depth vessels or other tissues can be attained. The mixed-signal PA SoC paves the way for sustainable health monitoring and owns immense potential for early disease diagnostics based on in vivo blood temperature sensing and vessel imaging.

A 12th-order active-RC bandpass filter (BPF) for a synthetic aperture radar (SAR) receiver is presented in this paper. The proposed BPF is composed of six cascaded Biquads and each Biquad is configured as a second-order bandpass stage and the switched resistor and capacitor arrays are used in the Biquad to enable the digital control of the passband center frequency and bandwidth. To achieve desired passband and behave with Chebyshev response, the capacitors in the six Biquads are designed with the same values and resistor values are tunable. The filter has been implemented in a 65 nm CMOS technology and achieved low ripple, low noise and low power consumption. Under 8-bit digital programmable, the center frequency is tunable from 0.98 MHz to 4.83 MHz and the bandwidth is tunable from 0.66 MHz to 5 MHz, and it measures a maximum in-band frequency response deviation of <0.6dB while consuming $\leq$12mW at a 1.2 V supply.

A 1GHz configurable chirp modulation (CM) direct digital frequency synthesizer (DDFS) is presented and implemented in 65nm CMOS technology. This DDFS is designed to generate 70-86MHz chirp signal for X-band frequency modulated continuous wave (FMCW) radar system. The proposed design is composed of 64-bit frequency control word (FCW) serial peripheral interface bus (SPI) supported 20-bit frequency/phase accumulator and 10-bit linear/non-linear hybrid digital-to-analog convertor (DAC). This DDFS supports saw-tooth chirp mode and exhibits 20-900 μs time of chirp duration (TCD) and 1ms pulse recurrence frequency (PRF), dissipates 24mW@1GHz clock from a 1.2V supply. The DDFS core occupies 180μm×170μm area.

This paper presents a 2.4-6 GHz highly integrated broadband GaN power amplifier (PA) with three stages for 2.4-/5-GHz dual-band 802.11ax application. A compact external output matching network is introduced to realize broadband output matching, while reducing the loss of the output matching network and saving the chip area. A novel topology of coupled resonators is exploited for the broadband inter-stage matching to cover the 802.11ax bands from 2.4 to 6 GHz. In the proposed topology, the coupling between the primary and secondary resonators is through a series inductor and a series capacitor. Compared with other conventional coupled resonators, the proposed topology produces an additional complex pole, further extending the bandwidth. The PA was designed and fabricated in Wolfspeed 0.25- μm GaN-on-SiC technology. The implemented PA achieves a saturated output power (Psat) of 35.2-36.3 dBm with a maximum power added efficiency (PAE) of 38-53% from 2.4 to 6 GHz. When tested with an 80-MHz, 256-quadratic-amplitude modulation (QAM) 802.11ax signal, the PA delivers an average output power of 27.1 and 25.7-27.2 dBm with a PAE of 20.9% and 18.4-24.6% in the 2.4-GHz and 5-GHz wireless local area network (WLAN) bands, respectively, while meeting the specification of error vector magnitude (EVM) below -32 dB.

Using on-chip slow-wave transmission line (SW-TL) has paved a new way towards millimeter-wave (mm-wave) to terahertz (THz) low power and high speed inter-/intra-chip communications. This work presents an on-chip SW-TL featured by periodic comb-shape grooves with capability to strongly localize electric-field. A gradient groove structure is proposed to serve as the mode converter and performs the mode transformation between the quasi-TEM wave and the slow-wave with low return loss. Due to field confinement, when two SW-TL are only 2.4 μm apart, more than 19 dB crosstalk suppression is observed compared with two conventional TL with the same metal spacing. A dual-channel 160 GHz frequency-shift keying (FSK) transceiver is designed in 65 nm CMOS technology. The preliminary results show that by exploiting SW-TL as the silicon channel, the receiver can recover error-free 4 Gb/s dual-channel data, whereas the eye diagram of the transceiver using traditional transmission line (TL) is fully distorted. The transceiver consumes 36 mW DC power from a 1.2 V power supply.

High current, small area, and superior transient response LDO is gaining increasing attention for the battery-powered 5G mobile application. This paper presents an NMOS LDO realized in 0.13μm CMOS process featuring a 10mV undershoot and overshoot with 1A/100ns load current. The superior transient performance is achieved by a new multi-loop feedback scheme. The presented LDO also embodies a new frequency compensation scheme, which enables a stable 60dB dc loop gain despite 1A load current variation. This contributes to a small load regulation and line regulation of 0.6μV/A and 0.23mV/V, respectively. The LDO consumes 35μA quiescent current in mission mode. The silicon size of the LDO is 325μm × 106μm.

The paper presents a two-stage cascade push-pull power amplifier (PA) with floating-body transistors in 130 nm Silicon-On-Insulator (SOI) CMOS process for IEEE 802.11ac application. In the proposed design, on chip baluns, which can realize impedance matching, are used in driver stage amplifier input and power stage amplifier output matching networks. The proposed PA can achieve high gain, high output power and wide bandwidth at the same time with 0.819mm2chip area including pads. With 2.5 V supply voltage, the implemented PA achieves 20.31 dB power gain with 3 dB bandwidth range from 3.9 GHz to 6.19 GHz, 20.96 dBm output power at 1 dB compression point (OP-1dB) and 9.85% power added efficiency (PAE).

In this paper, a delay locked loop (DLL) based configurable multi-phase clock generator with wide operating range and high resolution is proposed. It is implemented by adopting array of configurable DLLs and is able to generate multi-phase frequencies with true-time-delay, which is essential in a wideband FMCW phased array system. Fabricated in a 40nm CMOS process, the proposed multi-phase clock generator achieves configurable phase delay with high resolution of 7ps under varies of reference frequency from 400MHz to 2.5 GHz. The clock generator consumes 20.9mW from a 1.1V supply.

The paper presents a wideband, low-power chirp synthesizer for Ku-band FMCW radars. The DDS-driven ADPLL chirp synthesizer generates chirps up to 2GHz bandwidth. A low-power DDS is employed to generate a stepped reference frequency for ADPLL to ensure the long term chirp linearity, while the ADPLL fulfill the ramp-interpolating linearization by generating a narrow band chirp within the step frequency. The entire chirp benefits from the phase domain modulation and mitigates ADPLL loop bandwidth variation to achieve high linearity and low power. A novel adaptive ramping control scheme is adopted to ensure the chirp rate is constant after combining the narrow band chirp segments. By this two-stage chirp generation, a 2-GHz chirp is achieved with low relative frequency RMS error. Fabricated in a 65nm CMOS, the synthesizer generates a wideband chirp from 13.9GHz to 15.9GHz with configurable rate from 0.25 to 4GHz/ms, and consumes 53.8mW.