Content Addressable Memories (CAMs) are valuable components in applications where fast, highly-associative searches are required. While common SRAMs can be protected from soft-errors using error-correcting codes (ECC), CAMs are much harder to protect against such effects. The main problem is that the comparison of a stored memory word to a search word, when both are encoded by ECCs, is far too complicated and expensive to be performed directly by circuits at each row of the CAM. The proposed design uses a modified NAND-type, dual match-line organization which keeps track of up to 1 bit mismatch per row. As CAM words are encoded using an ECC of Hamming distance of 3, a single bit error can be "corrected" during the search operation, by ignoring any single-bit mismatch. The design is analyzed in detail with regard to charge-sharing noise, speed and power and the cost of error-tolerance is investigated against a state-of-the art NAND-type CAM. Compared against the best-known, error-tolerant CAM, which uses a NOR match-line organization, the proposed circuit is faster and more energy efficient.

This paper introduces a novel synchronous to asynchronous logic conversion tool targeted specifically for a synchronous field programmable gate array (FPGA). This tool augments the synchronous FPGA design flow and removes the clock network to implement an asynchronous control network in its place. We evaluate the timing performance benefits of the methods used to implement the asynchronous control network on synchronous FPGA fabric. Industrial video processing circuits are used to demonstrate the iterative timing improvements the tool makes to asynchronous control networks in each circuit. The targeted design constraints used in the tool are intended to improve the robustness and predictability of the placed circuits. This allows the timing benefits of asynchronous bundled data circuits easier to achieve, making asynchronous circuits a viable design option on modern FPGAs.

A novel test pattern generation method for asynchronous circuits is described and evaluated in detail. The method combines conventional pattern generation with hazard-free state initialization. Any type of asynchronous circuit can be processed, and all stuck-at faults, even those inside state-holding elements, such as C-elements, are considered. The results on some of the largest benchmarks ever used for asynchronous circuit testing show fault coverage on the order of 99% with no area overhead for (quasi-)delay-insensitive datapath circuits.

The advantages of power-aware processors are well known. This paper presents an innovative processor architecture optimized for wireless environments. The presented architecture incorporates a certain power-aware microarchitectural technique, called pipeline depth adaptation and it is tailored to self-timed processors. With this technique, a processor is able to alter its pipeline depth, while in operation, trading speed and energy use. The pipeline depth is changed by making selected pipeline registers transparent. A shallow pipeline has lower energy consumption for two reasons: the capacitance driven by the load signal of the 'collapsed' pipeline registers is not switched and the reduction in branch latency and data-dependent stalls reduce the cycles per instruction (CPI) of the processor. An analysis of the advantages of using pipeline depth adaptation in an asynchronous processor is given, supported by simulation results based on a real asynchronous processor and on applications that are frequently executed on a wireless environment. Finally, a method of dynamically adapting the pipeline depth is described and evaluated which only reduces the pipeline depth when a branch instruction is expected. The presented architecture has a relatively lower power consumption than a conventional similar architecture, therefore it can be useful in wireless environments.

A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for high n-variable (high fan-in) implementations, is presented. The checker is characterized by high testability, high operating frequencies and low silicon area requirements. The circuit has been designed, for various n-variable values, in a 0.18/spl mu/m technology and SPICE simulations have been carried out to validate its operation.

Asynchronous design offers a solution to the interconnect problems faced by system-on-chip (SoC) designers, but their adoption has been held back by a lack of methodology and support for post-fabrication testing. This paper first addresses the problem of testing C-elements, an important building block of asynchronous circuits. A simple method for generating test patterns is described which is shown to be applicable for a wide range of implementations. Based on the C-element testability, a partial scan technique was developed that achieves a test coverage of over 99.5% when applied to an asynchronous, network-on-chip, interconnect fabric. Test patterns are automatically generated by a custom program, given the interconnect topology. Area savings of at least 60% are noted, in comparison to standard, asynchronous, full-scan level-sensitive scan devices (LSSD) methods.

Asynchronous circuits offer great potential for solving the interconnect problems faced by system-on-chip designers, but their adoption has been held back by a lack of methodology and support for fabrication testing of such circuits. This paper addresses this problem using a partial scan approach which achieves a test coverage of 99.5% on the CHAIN network-on-chip interconnect fabric which is used as an example. Test patterns are generated by a custom program automatically, given the topology of the interconnect. In comparison to standard, asynchronous, full-scan LSSD methods, area savings in the order of 50% are noted.

This paper presents 3/spl Phi/LSSD, a novel, easily-automatable approach for scan insertion and ATPG of asynchronous circuits. 3/spl Phi/LSSD inserts scan latches only into global circuit feedback paths, leaving the local feedback paths of asynchronous state-storing gates intact. By employing a three-phase LSSD clocking scheme and complemented by a novel ATPG method, our approach achieves industrial quality testability with significantly less area overhead testing the same number of faults compared to full-scan LSSD. The effectiveness of our approach is demonstrated on an asynchronous SOC interconnection fabric, where our 3/spl Phi/LSSD ATPG tool achieved over 99% test coverage.

A novel, low-energy content addressable memory (CAM) structure is presented which achieves an approximately four-fold improvement in energy per access, compared to a standard parallel CAM, when used as tag storage for caches. It exploits the address patterns commonly found in application programs, where testing the four least significant bits of the tag is sufficient to determine over 90% of the tag mismatches; the proposed CAM checks those bits first and evaluates the remainder of the tag only if they match. Although, the energy savings come at the cost of a 25% increase in search time, the proposed CAM organization also supports a parallel operating mode without a speed loss but with reduced energy savings.

A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the method is applied to applications with slack time, the user-perceived performance may not be degraded Two techniques are shown using an existing asynchronous processor as a starting point. The first method controls the pipeline occupancy using a token mechanism, the second enables adjacent pipeline stages to be merged, by making the latches between them 'permanently' transparent. An energy reduction of up to 16% is measured, using a collection of five benchmarks.

There is an on-going debate about which consumes less energy: a RAM-tagged associative cache with an intelligent order of accessing its tags and ways (e.g. way prediction), or a CAM-tagged high associativity cache. If a CAM search can consume less than twice the energy of reading a tag RAM, it would probably be the preferred option for low-power applications. Based on memory traces --- which usually cause tag mismatch within the lower four bits --- a new serial CAM organisation is proposed which consumes just 45% more than a single tag RAM read and is only 25% slower than the conventional, parallel CAM. Furthermore, it can optionally be operated as a parallel CAM, at no speed penalty, and still reduce energy consumption.

Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perform better than multiple input queues or buffers, and the VLSI implementation of the former is not more expensive than the latter. We present a new organization for a shared buffer with its associated switching and cut-through functions. It is simpler and smaller than wide or interleaved organizations, and it is particularly suitable for VLSI technologies. It is based on multiple memory banks, addressed in a pipelined fashion. The first word of a packet is transferred to/from the first bank, followed by a "wave" of similar operations for the remaining words in the remaining banks. An FPGA-based prototype is operational, while standard-cell and full-custom chips are being submitted for fabrication. Simulation of the full-custom version indicates that, even in a conservative 1-micron CMOS technology, a 64 Kbit central buffer for an 8×8 switch operates at 1 Gbps/link (worst case) and fits in 45 mm2 including crossbar and cut-through.