This book deals with a very important topic in computer engineering techniques, i.e., the use of digital computers as design tools in the development of digital systems. The use of design automation has been rapidly gaining wide acceptance, especially in recent years, in the computer industry due to the rapid pace of changing technologies and the desirability of shortening design and manufacturing intervals. While a number of significant results in design automation have been realized, most are either scattered in various literatures or are not readily obtainable. This book, written by eight authors, represents a body of information where several phases of design automation techniques, i.e., logic synthesis, logic simulation, testing, and physical implementation (partitioning, placement, and routing) are discussed.

A comparison of the central processing unit (CPU) time and storage requirements for the parallel and deductive fault simulation techniques is presented. Versions of a parallel and deductive simulator were implemented and the comparison performed on an IBM System/360 Model 67 by simulating representative circuits including shift registers, sequencers, counters, two memory units, and a processor. The results indicate that the deductive technique requires less CPU time for "loosely sequential" circuits or circuits having large numbers of simulated faults (e.g., >1000). The parallel technique is faster for small (e.g., <500 gates) "highly sequential" circuits or for small numbers of simulated faults. The storage required for a parallel simulator, however, can always be less than that required for a deductive simulator. In general, if sufficient memory is available, the deductive simulator is the more cost-effective simulator when a wide range of circuits is to be simulated and only one type of simulator is available. A substantial savings in logic circuit development cost can be realized when the proper simulation technique is used for logic design verification, fault analysis, and the generation of diagnostic data.

This paper describes the internal workings of a low-cost microprogrammed processor designed to control electronic switching systems. The machine is structurally regular to ease maintenance difficulties and allow more efficient packaging.

This paper describes the various fault detection, routine exercise, and diagnostic techniques used in the design of a switching complex. Unlike other electronic switching system (ESS) processors, the processor is entirely self-checking.

This is an interesting paper. The authors consider two problems related to the testing of universal cellular tree circuits. The first is concerned with the detection and location of faulty cells by applying a minimal number of tests. The second is concerned with that of finding a set of switching functions that can be implemented by a faulty tree circuit.

In the design of combinational diagnostic testing procedure for a large digital system, some redundant tests are expected. This paper describes an algorithm for selecting a good (locally optimized) set of diagnostic tests which contains no redundancy. The algorithm will in general tend to give a ``fairly good'' set of test patterns, but is not guaranteed to be absolutely minimal. An overall optimization scheme is desirable but seems impractical [1]. The procedure described can be used either to yield a set of diagnostics which loses no resolution from the full set, or to yield a smaller set with some loss in resolution.