The problem of fault grading for multiple path delay faults is introduced and a method of obtain exact coverage is presented. The faults are represented and manipulated as combinational sets using zero-suppressed binary decision diagrams. The presented methodology for fault grading uses only a polynomial number of zero-suppressed binary decision diagram operations. The efficiency of the proposed method is demonstrated by the experimental results on the ISCAS'85 and ISCAS'89 benchmarks.

We present a novel framework to identify all the testable and untestable path delay faults (PDFs) in a circuit. The method uses a combination of decision diagrams for manipulating PDFs as well as Boolean functions. The approach benefits from processing partial paths or fanout-free segments in the circuit rather than the entire path. The methodology is modified to identify all testable critical PDFs under the bounded delay fault model. The effectiveness of the proposed framework is demonstrated experimentally. It is observed that the methodology outperforms any existing method for identifying testable PDFs. Its scalability by focusing on critical PDFs is demonstrated by experimenting on very path-intensive benchmarks.

We present a novel framework to identify all the robustly testable and untestable path delay faults in a circuit. The method uses a combination of decision diagrams for manipulating path delay faults and Boolean functions. The approach benefits from processing partial paths or fanout free segments in the circuit rather than the entire path. The effectiveness of the proposed framework is demonstrated experimentally. It is observed that the methodology identifies 350% more testable faults in the ISCAS'85 benchmark C6288 than any existing technique by utilizing only a fraction of the time compared to earlier work.

In this paper we propose an implicit test pattern generation method so that many path delay faults are covered and the dissipated power satisfies a given bound. Typical delay values are considered from an accurate gate delay model. We use a timed ATPG that combines function-based and structural (PODEM-like) methods for faster test generation, which is also more accurate in sequential circuits.

An approach for selecting critical paths along which testable path delay faults can exist is presented. The proposed method is particularly helpful on path intensive circuits. Critical paths are selected implicitly with the aid of a combination of decision diagrams. An implicit method to eliminate untestable faults along the selected paths is also presented. The effectiveness of the approach is demonstrated on path intensive ISCAS'85, ISCAS'89 and ITC'99 benchmarks.

We formulate the path delay fault (PDF) coverage problem as a combinatorial problem that amounts to storing and manipulating sets using a special type of binary decision diagrams, called zero-suppressed binary decision diagrams (ZBDD). The ZBDD is a canonical data structure inherently having the property of representing combinational sets very compactly. A simple modification of the proposed basic scheme allows us to increase significantly the storage capability of the data structure with minimal loss in the fault coverage accuracy. Experimental results on the ISCAS85 benchmarks show considerable improvement over all existing techniques for exact PDF grading. The proposed methodology is simple, it consists of a polynomial number of increasingly efficient ZBDD-based operations, and can handle very large test sets that grade very large number of faults.

The first nonenumerative framework for diagnosing path delay faults (PDFs) using zero suppressed binary decision diagrams is introduced. We show that fault-free PDFs with certain validated nonrobust test may be used together with fault-free robustly tested faults to eliminate faults from the set of suspected faults. All operations are implemented by an implicit diagnosis tool based on the zero-suppressed binary decision diagram. The proposed method is space and time nonenumerative as opposed to existing methods which are space and time enumerative. Experimental results on the ISCAS'85 benchmarks show that the proposed technique is on average three times more efficient than the existing techniques.

The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulated as sets by zero-suppressed binary decision diagrams (ZBDD), which are shown to be able to store a very large number of path delay faults. For the extreme case of memory problem, a method to estimate the coverage of the test set is also presented. The problem of fault grading is solved with a polynomial number of BDD operations. Experimental results on the ISCAS'85 benchmark include test sets from ATPG tools and specifically designed tests in order to investigate the limitations and properties of the proposed method.

Formulates the fault grading problem as a combinatorial problem that amounts to storing and manipulating sets on a special type of binary decision diagrams (BDDs), called zero-suppressed BDDs (ZBDDs), that represent sets in a unique and compact manner. A simple modification of the basic scheme allows us to overcome memory problems that may arise by complex set representation. Experimental results on the ISCAS'85 benchmarks show considerable improvement over all existing techniques for exact PDF grading. The main advantages of the proposed methodology are the simplicity of the approach, in terms of it being expressed by a polynomial number of increasingly efficient BDD-based operations, its organization, and its ability to handle very large test sets.