A novel distributed-resource abstraction environment is introduced. You can access any resource in a computer network as a memory mapped I/O device, as if it was attached to the local bus of your PC. This network technology gives us several benefits. From the application development viewpoint, no network-related programming is required, and we don't need to modify the applications even if the network topologies and protocols are changed. On the other hand, network maintenance and upgrading can be done anytime without worrying about the application users, because the environment completely separates or hides the network from the applications. The API (Application Program Interface), a resource abstraction mechanism, and a directory service are implemented. In addition, a reconfigurable hardware technology is adopted to perform autonomous network control using a lour layer protocol. Furthermore, we introduce a testbed that allows heterogeneous resources to be utilized, and demonstrate the feasibility of our concept using some applications.

This paper discusses how a distributed environment providing effortless networking can be efficiently implemented in a network system. To formalize the distributed environment, we introduce the concept of "Virtual BUS". It is similar to the concept of the computer system's bus architecture. We define user behavior as accessing the resources in a network through his/her own bus. Based on this simple formalization, we discuss the key issues in implementing distributed environments to support different requirements for realizing the quality of service desired. We implement an experimental effortless networking environment based on the Virtual BUS concept and show that the concept realizes effortless networking while guaranteeing QoS.

In this paper, we propose an efficient path selection method for path delay testing. The proposed method selects a very small set of paths for delay testing that covers all paths. Path selection is done by judging which of two paths has the larger real delay by taking into account the ambiguity of calculated delay, caused by imprecise delay modeling as well as process disturbance. In order to make precise judgement under this ambiguity, the delays of only unshared segments between the two paths are evaluated. This is because the shared segments are presumed to have the same real delays on both paths. Experimental results show the method can select about one percent of the paths selected by a conventional method without decreasing fault coverage.

Several requirements must be satisfied to generate test patterns for scan designs. One important requirement is to prevent scan-in values from being destroyed. This is necessary to avoid unexpected asynchronous behavior as well as bus clash after applying the capture clock. This paper shows that constrained test pattern generation is very effective for this purpose. The constraints introduced in this paper change dynamically depending on values of the circuit. They are imposed on the pseudo-primary inputs or the pseudo-primary outputs so that the scan-in values are held after applying the capture clock. The patterns generated with the constraints are guaranteed to be valid even when a hazard occurs. Experimental results using actual devices show the efficiency of the proposed method.

This paper presents a signature analysis method that achieves a minimum aliasing rate. A fault stay map derived from exact fault simulation without fault dropping indicates whether a fault remains in an output data compressor at each time step. The fault stay map is used to determine the timing of multiple signature observations to achieve the minimum aliasing rate under certain constraints. Experimental results for some combinational circuits modeled on a single stuck-at fault are presented. They show that only two signature observations are required to achieve 0% aliasing in almost all circuits.>

A scientific parallel processor called the R256 has been developed. The R256 is composed of 16x16 processing elements, and has the outstanding features of a “distributed parallel network” as well as on IEEE 80-bit extended floating point computation ability. The computation accuracy, required by an exhaustive number of iterations in scientific computations, is resolved by the dedicated 80-bit VLSI processor, which was developed here for the R256. The innovative distributed parallel network was designed so as to effectively resolve heavy communication problems, which are found in applications based on the Monte Carlo simulation technique. The R256 network was very economical at a hardware cost of √N-folds (16 folds in this case) to that of an ideal full-crossbar switch, at the same time keeping the rates comparable to that of an ideal switch. The R256 demonstrates high performance of 2-GB/s data transfer rates and 500-MFLOPS computation rates on a semiconductor device simulation application.