For nanometer design, conventional timing analysis may generate over-optimistic results on criticality-dependent paths. A late arrival time at the data input of a flip-flop lengthens the propagation delay from the clock pin to the data output of this flip-flop, thus degrading the timing margins of paths launching from this flip-flop. To remove the optimism, in this paper, we first propose a simple yet effective triangle model to characterize the criticality-dependency effect. Then, we devise a novel criticality-dependency-aware timing analysis flow, which is seamlessly integrated with the common static timing analysis flow. Experimental results show that our approach can effectively analyze the criticality-dependency effect: Based on the proposed triangle model, we can accurately identify all timing-risky flip-flops and capture the induced timing margin degradation.

Newest manufacturing technologies with feature sizes smaller than 20nm and FinFET devices have favored more restrictive design rules for manufacturability while suffering from electrical limitations of electromigration (EM) and variability. Designers can no longer reap the benefits in power, performance and area by simply relying on feature size miniature with contemporary design techniques. This work illustrates the importance of design and manufacturing technology co-optimization. Limitations in lithography has led to slower reduction in metal and VIA shape spacing than critical dimensions, which prompts for co-optimization in metallization stack, power mesh planning, standard cell designs and placement algorithms. New routing algorithms and parasitics modeling are required to achieve improved design performance under sky-rocketing metal resistance especially at lower metal levels. Ever-lowering maximum current limits due to EM has prompted new approaches in placement optimization to counteract the potential explosion in EM violations. Adoption of FinFET has allowed ultra-low Vdd designs, which requires careful consideration of Vth offerings that allow proper trade-off between variability, area and power efficiency.

In this paper we review the prior art and recent advances in the area of standard cell modeling for delay and noise analyses, suggest a taxonomy of different cell models, and discuss their strengths and weaknesses. We also discuss challenges in cell modeling for delay and noise analyses arising in new submicron process nodes.

This paper presents the first in-depth study on dual-Vddbuffer insertion for power minimization under delay constraint. Compared with delay-optimal singleVddbuffer insertion, the dual-Vddbuffer insertion reduces power by 16%. Such power reduction increases when the delay specification is relaxed. Whereas the van Ginneken algorithm can be extended to handle the new problem formulation optimally, its time complexity increases from quadratic time (O(|B|n2)) to pseudopolynomial time (O(|B|n3cmax2log(ncmax)), where |B| is the size of buffer library,nis the number of buffer stations, andcmaxis proportional to the number of all possible subtrees of the net. To improve the time complexity, we propose an approximation technique by sampling subsolutions (i.e., options) and apply predictive min-delay and prebuffer slack pruning rules from a related work. Experiments show that sampling is most effective to reduce run time, whereas the two pruning rules further improve efficiency and accuracy loss due to sampling. We show that our proposed algorithm has linear time complexity with respect to the tree size. It runs over 1000 times faster at a cost of less than 2% delay and power increase over the extended van Ginneken algorithm.

Abstract—This paper presents extensions of the dynamicprogramming (DP) framework to consider buffer insertion and wire-sizing under effects of process variation. We study the effectiveness of this approach to reduce timing impact caused by chemical–mechanical planarization (CMP)-induced systematic variation and random Leffprocess variation in devices. We first present a quantitative study on the impact of CMP to interconnect parasitics. We then introduce a simple extension to handle CMP effects in the buffer insertion and wire sizing problem by simultaneously considering fill insertion (SBWF).We also tackle the same problem but with random Leffprocess variation (vSBWF) by incorporating statistical timing into the DP framework. We develop an efficient yet accurate heuristic pruning rule to approximate the computationally expensive statistical problem. Experiments under conservative assumption on process variation show that SBWF algorithm obtains 1.6% timing improvement over the variationunaware solution. Moreover, our statistical vSBWF algorithm results in 43.1% yield improvement on average. We also show that our approaches have polynomial time complexity with respect to the net-size. The proposed extensions on the DP framework is orthogonal to other power/area-constrained problems under the same framework, which has been extensively studied in the literature.

This paper presents the first in-depth study on applying dual VDD buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constraint. To tackle the problem of dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices, we develop a sampling-based sub-solutions (i.e. options) propagation method and a balanced search tree-based data structure for option pruning. We obtain 17x speedup with little loss of optimality compared to the exact option propagation. Moreover, compared to buffer insertion with single VDD buffers, dual-VDD buffers reduce power by 23% at the minimum delay specification. In addition, compared to the delay-optimal tree using single VDD buffers, our power-optimal buffered tree reduces power by 7% and 18% at the minimum delay specification when single VDD and dual VDD buffers are used respectively.

A comprehensive probabilistic methodology is proposed to solve the buffer insertion problem with the consideration of process variations. In contrast to a recent work, we point out, for the first time, that the correlation between the required arrival time and the downstream loading capacitance must be considered in order to solve the problem "correctly". We develop an efficient bottom-up recursive algorithm to calculate the joint probability density function that accurately captures the above correlation, and propose effective pruning rules to exclude probabilistically inferior solutions. We verify our buffer insertion using timing analysis with both device and interconnect variations, and show that compared to the conventional buffer insertion algorithm using nominal device and interconnect parameters, our new buffer insertion methodology can reduce the probability of timing violation by up to 30%.

This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion lengths, repeater sizes, and Vdd and Vth levels for a net with a delay target, and it reduces more than 50 % power over a previous work which does not consider Vdd and Vth optimization. This work further presents the power saving when multiple Vdd and Vth levels are used in repeater insertion at the full-chip level. Compared to the case with single Vdd and Vth suggested by ITRS, optimized dual Vdd and dual Vth reduce overall global interconnect power by 47%, 28% and 13 % for 130nm, 90nm and 65nm technology nodes, respectively, but extra Vdd or Vth levels only give marginal improvement. We also show that an optimized single Vth reduce interconnect power almost as effective as dual-Vth does, in contrast to the need of dual Vth for logic circuits.

Abstract—This paper presents extensions of the dynamic-programming (DP) framework to consider buffer insertion and wire-sizing under effects of process variation. We study the effectiveness of this approach to reduce timing impact caused by chemical–mechanical planarization (CMP)-induced systematic variation and random Leff process variation in devices. We first present a quantitative study on the impact of CMP to interconnect parasitics. We then introduce a simple extension to handle CMP effects in the buffer insertion and wire sizing problem by simulta-neously considering fill insertion (SBWF). We also tackle the same problem but with random Leff process variation (vSBWF) by in-corporating statistical timing into the DP framework. We develop an efficient yet accurate heuristic pruning rule to approximate the computationally expensive statistical problem. Experiments under conservative assumption on process variation show that SBWF algorithm obtains 1.6 % timing improvement over the variation-unaware solution. Moreover, our statistical vSBWF algorithm results in 43.1 % yield improvement on average. We also show that our approaches have polynomial time complexity with respect to the net-size. The proposed extensions on the DP framework is orthogonal to other power/area-constrained problems under the same framework, which has been extensively studied in the literature. Index Terms—Buffering, dummy fill insertion, fill patterns, interconnect optimization, process variation, random Leff variation, systematic CMP variation, wire sizing. I.